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git01.mediatek.com / filogic / uboot / 914be13dfc6fb691b7d7a5ba90fd6cfad08440e4 / . / board / dbau1x00 / dbau1x00.c
blob: 315e412605c8bcc10560149b40ac46b0d54a83bd [file] [log] [blame]
wdenk9b7f3842003-10-09 20:09:04 +0000[diff] [blame]1/*
2 * (C) Copyright 2003
3 * Thomas.Lange@corelatus.se
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <asm/au1x00.h>
27#include <asm/mipsregs.h>
28
29long int initdram(int board_type)
30{
31 /* Sdram is setup by assembler code */
32 /* If memory could be changed, we should return the true value here */
33 return 64*1024*1024;
34}
35
36#define BCSR_PCMCIA_PC0DRVEN 0x0010
37#define BCSR_PCMCIA_PC0RST 0x0080
38
39/* In cpu/mips/cpu.c */
40void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
41
42int checkboard (void)
43{
44 u16 status;
45 volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10);
46 volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC);
47 volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
48 u32 proc_id;
49
50 *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
51
52 proc_id = read_32bit_cp0_register(CP0_PRID);
53
wdenk4ea537d2003-12-07 18:32:37 +0000[diff] [blame]54 switch (proc_id >> 24) {
wdenk9b7f3842003-10-09 20:09:04 +0000[diff] [blame]55 case 0:
wdenk4ea537d2003-12-07 18:32:37 +0000[diff] [blame]56 puts ("Board: Merlot (DbAu1000)\n");
57 printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
58 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
59 break;
60 case 1:
61 puts ("Board: DbAu1500\n");
62 printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
63 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
64 break;
65 case 2:
66 puts ("Board: DbAu1100\n");
67 printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
68 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
69 break;
wdenk9b7f3842003-10-09 20:09:04 +0000[diff] [blame]70 default:
wdenk4ea537d2003-12-07 18:32:37 +0000[diff] [blame]71 printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
wdenk9b7f3842003-10-09 20:09:04 +0000[diff] [blame]72 }
73#ifdef CONFIG_IDE_PCMCIA
74 /* Enable 3.3 V on slot 0 ( VCC )
75 No 5V */
76 status = 4;
77 *pcmcia_bcsr = status;
78
79 status |= BCSR_PCMCIA_PC0DRVEN;
80 *pcmcia_bcsr = status;
81 au_sync();
82
83 udelay(300*1000);
84
85 status |= BCSR_PCMCIA_PC0RST;
86 *pcmcia_bcsr = status;
87 au_sync();
88
89 udelay(100*1000);
90
91 /* PCMCIA is on a 36 bit physical address.
92 We need to map it into a 32 bit addresses */
93
94#if 0
95 /* We dont need theese unless we run whole pcmcia package */
96 write_one_tlb(20, /* index */
97 0x01ffe000, /* Pagemask, 16 MB pages */
98 CFG_PCMCIA_IO_BASE, /* Hi */
99 0x3C000017, /* Lo0 */
100 0x3C200017); /* Lo1 */
101
102 write_one_tlb(21, /* index */
103 0x01ffe000, /* Pagemask, 16 MB pages */
104 CFG_PCMCIA_ATTR_BASE, /* Hi */
105 0x3D000017, /* Lo0 */
106 0x3D200017); /* Lo1 */
107#endif
108 write_one_tlb(22, /* index */
109 0x01ffe000, /* Pagemask, 16 MB pages */
110 CFG_PCMCIA_MEM_ADDR, /* Hi */
111 0x3E000017, /* Lo0 */
112 0x3E200017); /* Lo1 */
113
114 /* Release reset of ethernet PHY chips */
115 /* Always do this, because linux does not know about it */
116 *phy = 3;
117
118 return 0;
119#endif
120}