blob: d77b4c4ab9c88780a5963abfd76061c09328caed [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -07002/*
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +02003 * Copyright (c) 2016-2018 Toradex, Inc.
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -07004 */
5
6#include <common.h>
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +02007#include <dm.h>
Simon Glassed38aef2020-05-10 11:40:03 -06008#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070011#include <asm/arch-tegra/ap.h>
12#include <asm/gpio.h>
13#include <asm/io.h>
14#include <asm/arch/gpio.h>
15#include <asm/arch/pinmux.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060016#include <env_internal.h>
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020017#include <pci_tegra.h>
Simon Glassdbd79542020-05-10 11:40:11 -060018#include <linux/delay.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070019#include <power/as3722.h>
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020020#include <power/pmic.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070021
22#include "../common/tdx-common.h"
23#include "pinmux-config-apalis-tk1.h"
24
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020025#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6)
26#define LAN_RESET_N TEGRA_GPIO(S, 2)
Igor Opaniukfeb8c0d2019-08-01 11:06:32 +030027#define FAN_EN TEGRA_GPIO(DD, 2)
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020028#define LAN_WAKE_N TEGRA_GPIO(O, 5)
29#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
30#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
31#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
32#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
Marcel Ziswiler46eb7292019-08-09 13:21:46 +030033#define VCC_USBH TEGRA_GPIO(T, 6)
34#define VCC_USBH_V1_0 TEGRA_GPIO(N, 5)
35#define VCC_USBO1 TEGRA_GPIO(T, 5)
36#define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4)
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070037
38int arch_misc_init(void)
39{
40 if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
41 NVBOOTTYPE_RECOVERY)
42 printf("USB recovery mode\n");
43
Marcel Ziswiler46eb7292019-08-09 13:21:46 +030044 /* PCB Version Indication: V1.2 and later have GPIO_PV0 wired to GND */
45 gpio_request(TEGRA_GPIO(V, 0), "PCB Version Indication");
46 gpio_direction_input(TEGRA_GPIO(V, 0));
47 if (gpio_get_value(TEGRA_GPIO(V, 0))) {
48 /*
49 * if using the default device tree for new V1.2 and later HW,
50 * use version for older V1.0 and V1.1 HW
51 */
52 char *fdt_env = env_get("fdt_module");
53
54 if (fdt_env && !strcmp(FDT_MODULE, fdt_env)) {
55 env_set("fdt_module", FDT_MODULE_V1_0);
56 printf("patching fdt_module to " FDT_MODULE_V1_0
57 " for older V1.0 and V1.1 HW\n");
58#ifndef CONFIG_ENV_IS_NOWHERE
59 env_save();
60#endif
61 }
62
63 /* activate USB power enable GPIOs */
64 gpio_request(VCC_USBH_V1_0, "VCC_USBH");
65 gpio_direction_output(VCC_USBH_V1_0, 1);
66 gpio_request(VCC_USBO1_V1_0, "VCC_USBO1");
67 gpio_direction_output(VCC_USBO1_V1_0, 1);
68 } else {
69 /* activate USB power enable GPIOs */
70 gpio_request(VCC_USBH, "VCC_USBH");
71 gpio_direction_output(VCC_USBH, 1);
72 gpio_request(VCC_USBO1, "VCC_USBO1");
73 gpio_direction_output(VCC_USBO1, 1);
74 }
75
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070076 return 0;
77}
78
79int checkboard(void)
80{
81 puts("Model: Toradex Apalis TK1 2GB\n");
82
83 return 0;
84}
85
86#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
87int ft_board_setup(void *blob, bd_t *bd)
88{
89 return ft_common_board_setup(blob, bd);
90}
91#endif
92
93/*
94 * Routine: pinmux_init
95 * Description: Do individual peripheral pinmux configs
96 */
97void pinmux_init(void)
98{
99 pinmux_clear_tristate_input_clamping();
100
101 gpio_config_table(apalis_tk1_gpio_inits,
102 ARRAY_SIZE(apalis_tk1_gpio_inits));
103
104 pinmux_config_pingrp_table(apalis_tk1_pingrps,
105 ARRAY_SIZE(apalis_tk1_pingrps));
106
107 pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
108 ARRAY_SIZE(apalis_tk1_drvgrps));
109}
110
111#ifdef CONFIG_PCI_TEGRA
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200112/* TODO: Convert to driver model */
113static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700114{
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700115 int err;
116
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200117 if (sd > 6)
118 return -EINVAL;
119
120 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700121 if (err) {
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200122 pr_err("failed to update SD control register: %d", err);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700123 return err;
124 }
125
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200126 return 0;
127}
128
129/* TODO: Convert to driver model */
130static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
131{
132 int err;
133 u8 ctrl_reg = AS3722_LDO_CONTROL0;
134
135 if (ldo > 11)
136 return -EINVAL;
137
138 if (ldo > 7) {
139 ctrl_reg = AS3722_LDO_CONTROL1;
140 ldo -= 8;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700141 }
142
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200143 err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo);
144 if (err) {
145 pr_err("failed to update LDO control register: %d", err);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700146 return err;
147 }
148
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200149 return 0;
150}
151
152int tegra_pcie_board_init(void)
153{
154 struct udevice *dev;
155 int ret;
156
157 ret = uclass_get_device_by_driver(UCLASS_PMIC,
158 DM_GET_DRIVER(pmic_as3722), &dev);
159 if (ret) {
160 pr_err("failed to find AS3722 PMIC: %d\n", ret);
161 return ret;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700162 }
163
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200164 ret = as3722_sd_enable(dev, 4);
165 if (ret < 0) {
166 pr_err("failed to enable SD4: %d\n", ret);
167 return ret;
168 }
169
170 ret = as3722_sd_set_voltage(dev, 4, 0x24);
171 if (ret < 0) {
172 pr_err("failed to set SD4 voltage: %d\n", ret);
173 return ret;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700174 }
175
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200176 gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N");
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700177 gpio_request(LAN_RESET_N, "LAN_RESET_N");
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200178 gpio_request(LAN_WAKE_N, "LAN_WAKE_N");
179
180#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
181 gpio_request(PEX_PERST_N, "PEX_PERST_N");
182 gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
183#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700184
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200185 return 0;
186}
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700187
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200188void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
189{
190 int index = tegra_pcie_port_index_of_port(port);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700191
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200192 if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */
193 struct udevice *dev;
194 int ret;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700195
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200196 ret = uclass_get_device_by_driver(UCLASS_PMIC,
197 DM_GET_DRIVER(pmic_as3722),
198 &dev);
199 if (ret) {
200 debug("%s: Failed to find PMIC\n", __func__);
201 return;
202 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700203
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200204 /* Reset I210 Gigabit Ethernet Controller */
205 gpio_direction_output(LAN_RESET_N, 0);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700206
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200207 /*
208 * Make sure we don't get any back feeding from DEV_OFF_N resp.
209 * LAN_WAKE_N
210 */
211 gpio_direction_output(LAN_DEV_OFF_N, 0);
212 gpio_direction_output(LAN_WAKE_N, 0);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700213
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200214 /* Make sure LDO9 and LDO10 are initially enabled @ 0V */
215 ret = as3722_ldo_enable(dev, 9);
216 if (ret < 0) {
217 pr_err("failed to enable LDO9: %d\n", ret);
218 return;
219 }
220 ret = as3722_ldo_enable(dev, 10);
221 if (ret < 0) {
222 pr_err("failed to enable LDO10: %d\n", ret);
223 return;
224 }
225 ret = as3722_ldo_set_voltage(dev, 9, 0x80);
226 if (ret < 0) {
227 pr_err("failed to set LDO9 voltage: %d\n", ret);
228 return;
229 }
230 ret = as3722_ldo_set_voltage(dev, 10, 0x80);
231 if (ret < 0) {
232 pr_err("failed to set LDO10 voltage: %d\n", ret);
233 return;
234 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700235
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200236 /* Make sure controller gets enabled by disabling DEV_OFF_N */
237 gpio_set_value(LAN_DEV_OFF_N, 1);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700238
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200239 /*
240 * Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype
241 * V1.0A and sample V1.0B and newer modules
242 */
243 ret = as3722_ldo_set_voltage(dev, 9, 0xff);
244 if (ret < 0) {
245 pr_err("failed to set LDO9 voltage: %d\n", ret);
246 return;
247 }
248 ret = as3722_ldo_set_voltage(dev, 10, 0xff);
249 if (ret < 0) {
250 pr_err("failed to set LDO10 voltage: %d\n", ret);
251 return;
252 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700253
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200254 /*
255 * Must be asserted for 100 ms after power and clocks are stable
256 */
257 mdelay(100);
258
259 gpio_set_value(LAN_RESET_N, 1);
260 } else if (index == 0) { /* Apalis PCIe */
261#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
262 /*
263 * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
264 * Evaluation Board
265 */
266 gpio_direction_output(PEX_PERST_N, 0);
267 gpio_direction_output(RESET_MOCI_CTRL, 0);
268
269 /*
270 * Must be asserted for 100 ms after power and clocks are stable
271 */
272 mdelay(100);
273
274 gpio_set_value(PEX_PERST_N, 1);
275 /*
276 * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
277 * Until 900 us After PEX_PERST# De-assertion
278 */
279 mdelay(1);
280 gpio_set_value(RESET_MOCI_CTRL, 1);
281#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
282 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700283}
284#endif /* CONFIG_PCI_TEGRA */
Gerard Salvatella108d7392018-11-19 15:54:10 +0100285
286/*
Igor Opaniukfeb8c0d2019-08-01 11:06:32 +0300287 * Enable/start PWM CPU fan
288 */
289void start_cpu_fan(void)
290{
291 gpio_request(FAN_EN, "FAN_EN");
292 gpio_direction_output(FAN_EN, 1);
293}
294
295/*
Gerard Salvatella108d7392018-11-19 15:54:10 +0100296 * Backlight off before OS handover
297 */
298void board_preboot_os(void)
299{
300 gpio_request(TEGRA_GPIO(BB, 5), "BL_ON");
301 gpio_direction_output(TEGRA_GPIO(BB, 5), 0);
302}