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Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +00001/*
Sylvain Lemieuxeb48e2b2015-07-27 13:37:35 -04002 * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +00003 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +00005 */
6
7#include <common.h>
Albert ARIBAUD \(3ADEV\)391e1632015-03-31 11:40:43 +02008#include <netdev.h>
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +00009#include <asm/arch/cpu.h>
10#include <asm/arch/clk.h>
11#include <asm/arch/wdt.h>
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020012#include <asm/arch/sys_proto.h>
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +000013#include <asm/io.h>
14
15static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
16static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
17
18void reset_cpu(ulong addr)
19{
20 /* Enable watchdog clock */
21 setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
22
Sylvain Lemieuxeb48e2b2015-07-27 13:37:35 -040023 /* To be compatible with the original U-Boot code:
24 * addr: - 0: perform hard reset.
25 * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
26 if (addr == 0) {
27 /* Reset pulse length is 13005 peripheral clock frames */
28 writel(13000, &wdt->pulse);
29
30 /* Force WDOG_RESET2 and RESOUT_N signal active */
31 writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
32 | WDTIM_MCTRL_M_RES2, &wdt->mctrl);
33 } else {
34 /* Force match output active */
35 writel(0x01, &wdt->emr);
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +000036
Sylvain Lemieuxeb48e2b2015-07-27 13:37:35 -040037 /* Internal reset on match output (no pulse on "RESOUT_N") */
38 writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
39 }
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +000040
41 while (1)
42 /* NOP */;
43}
44
45#if defined(CONFIG_ARCH_CPU_INIT)
46int arch_cpu_init(void)
47{
48 /*
Bin Meng75574052016-02-05 19:30:11 -080049 * It might be necessary to flush data cache, if U-Boot is loaded
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +000050 * from kickstart bootloader, e.g. from S1L loader
51 */
52 flush_dcache_all();
53
54 return 0;
55}
56#else
57#error "You have to select CONFIG_ARCH_CPU_INIT"
58#endif
59
60#if defined(CONFIG_DISPLAY_CPUINFO)
61int print_cpuinfo(void)
62{
63 printf("CPU: NXP LPC32XX\n");
64 printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
65 printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
66 printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
67
68 return 0;
69}
70#endif
Albert ARIBAUD \(3ADEV\)391e1632015-03-31 11:40:43 +020071
72#ifdef CONFIG_LPC32XX_ETH
73int cpu_eth_init(bd_t *bis)
74{
75 lpc32xx_eth_initialize(bis);
76 return 0;
77}
78#endif