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git01.mediatek.com / filogic / uboot / 90fa4e9982e65dc7b55e5d3d90a61dd74690a2f9 / . / configs / am65x_hs_evm_r5_defconfig
blob: ead4a59c3874f3ce01940f996f2a93be556b997a [file] [log] [blame]
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_K3=y
3CONFIG_TI_SECURE_DEVICE=y
4CONFIG_SPL_GPIO_SUPPORT=y
5CONFIG_SPL_LIBCOMMON_SUPPORT=y
6CONFIG_SPL_LIBGENERIC_SUPPORT=y
Andreas Dannenberg355f0632019-06-04 17:55:52 -0500[diff] [blame]7CONFIG_SYS_MALLOC_F_LEN=0x55000
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]8CONFIG_SOC_K3_AM6=y
Andrew F. Davis6ed6be32020-03-10 11:08:41 -0400[diff] [blame]9CONFIG_K3_EARLY_CONS=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]10CONFIG_TARGET_AM654_R5_EVM=y
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]11CONFIG_ENV_SIZE=0x20000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]12CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]13CONFIG_DM_GPIO=y
Tom Rini6c75e632020-06-16 19:06:29 -0400[diff] [blame]14CONFIG_SPL_DM_SPI=y
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]15CONFIG_SPL_TEXT_BASE=0x41c00000
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]16CONFIG_SPL_MMC_SUPPORT=y
17CONFIG_SPL_SERIAL_SUPPORT=y
18CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
19CONFIG_SPL_STACK_R_ADDR=0x82000000
Tom Rinifdc7e362019-11-11 20:04:24 -0500[diff] [blame]20CONFIG_NR_DRAM_BANKS=2
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]21CONFIG_SPL_FS_FAT=y
22CONFIG_SPL_LIBDISK_SUPPORT=y
Vignesh Raghavendra040362f2020-02-04 11:09:58 +0530[diff] [blame]23CONFIG_SPL_SPI_FLASH_SUPPORT=y
24CONFIG_SPL_SPI_SUPPORT=y
Tom Rini90fa4e92020-07-06 15:46:38 -0400[diff] [blame^]25CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]26# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
27CONFIG_SPL_LOAD_FIT=y
28CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
29CONFIG_USE_BOOTCOMMAND=y
30# CONFIG_DISPLAY_CPUINFO is not set
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]31CONFIG_SPL_STACK_R=y
32CONFIG_SPL_SEPARATE_BSS=y
Andreas Dannenberg355f0632019-06-04 17:55:52 -0500[diff] [blame]33CONFIG_SPL_EARLY_BSS=y
Andreas Dannenberg598a7e12019-06-04 17:55:54 -0500[diff] [blame]34CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
35CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
Vignesh Raghavendra040362f2020-02-04 11:09:58 +0530[diff] [blame]36CONFIG_SPL_DMA=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]37CONFIG_SPL_I2C_SUPPORT=y
38CONFIG_SPL_DM_MAILBOX=y
Lukasz Majewski76f442982020-06-04 23:11:53 +0800[diff] [blame]39CONFIG_SPL_DM_SPI_FLASH=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]40CONFIG_SPL_DM_RESET=y
41CONFIG_SPL_POWER_SUPPORT=y
42CONFIG_SPL_POWER_DOMAIN=y
43CONFIG_SPL_RAM_SUPPORT=y
44CONFIG_SPL_RAM_DEVICE=y
45CONFIG_SPL_REMOTEPROC=y
Vignesh Raghavendra040362f2020-02-04 11:09:58 +0530[diff] [blame]46# CONFIG_SPL_SPI_FLASH_TINY is not set
47CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
48CONFIG_SPL_SPI_LOAD=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]49CONFIG_SPL_YMODEM_SUPPORT=y
50CONFIG_HUSH_PARSER=y
51CONFIG_CMD_BOOTZ=y
52CONFIG_CMD_ASKENV=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]53CONFIG_CMD_GPT=y
Andreas Dannenberg46051df2019-06-04 18:08:17 -0500[diff] [blame]54CONFIG_CMD_I2C=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]55CONFIG_CMD_MMC=y
56CONFIG_CMD_REMOTEPROC=y
57# CONFIG_CMD_SETEXPR is not set
58CONFIG_CMD_TIME=y
59CONFIG_CMD_FAT=y
60CONFIG_OF_CONTROL=y
61CONFIG_SPL_OF_CONTROL=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]62CONFIG_SPL_MULTI_DTB_FIT=y
63CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
64CONFIG_ENV_IS_IN_FAT=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]65CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]66CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]67CONFIG_DM=y
68CONFIG_SPL_DM=y
69CONFIG_SPL_DM_SEQ_ALIAS=y
Vignesh Raghavendra040362f2020-02-04 11:09:58 +0530[diff] [blame]70CONFIG_REGMAP=y
71CONFIG_SPL_REGMAP=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]72CONFIG_SPL_OF_TRANSLATE=y
73CONFIG_CLK=y
74CONFIG_SPL_CLK=y
75CONFIG_CLK_TI_SCI=y
Vignesh Raghavendra040362f2020-02-04 11:09:58 +0530[diff] [blame]76CONFIG_DMA_CHANNELS=y
77CONFIG_TI_K3_NAVSS_UDMA=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]78CONFIG_TI_SCI_PROTOCOL=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]79CONFIG_DA8XX_GPIO=y
Andreas Dannenberg46051df2019-06-04 18:08:17 -0500[diff] [blame]80CONFIG_DM_I2C=y
81CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
82CONFIG_SYS_I2C_OMAP24XX=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]83CONFIG_DM_MAILBOX=y
84CONFIG_K3_SEC_PROXY=y
Andrew F. Davis6ed6be32020-03-10 11:08:41 -0400[diff] [blame]85CONFIG_K3_AVS0=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]86CONFIG_DM_MMC=y
87CONFIG_MMC_SDHCI=y
Andrew F. Davis6ed6be32020-03-10 11:08:41 -0400[diff] [blame]88CONFIG_SPL_MMC_SDHCI_ADMA=y
89CONFIG_MMC_SDHCI_AM654=y
Vignesh Raghavendra040362f2020-02-04 11:09:58 +0530[diff] [blame]90CONFIG_DM_SPI_FLASH=y
91CONFIG_SPI_FLASH_SFDP_SUPPORT=y
92CONFIG_SPI_FLASH_STMICRO=y
93# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]94CONFIG_PINCTRL=y
95# CONFIG_PINCTRL_GENERIC is not set
96CONFIG_SPL_PINCTRL=y
97# CONFIG_SPL_PINCTRL_GENERIC is not set
98CONFIG_PINCTRL_SINGLE=y
99CONFIG_POWER_DOMAIN=y
100CONFIG_TI_SCI_POWER_DOMAIN=y
101CONFIG_DM_REGULATOR=y
102CONFIG_SPL_DM_REGULATOR=y
103CONFIG_DM_REGULATOR_GPIO=y
104CONFIG_SPL_DM_REGULATOR_GPIO=y
Andrew F. Davis6ed6be32020-03-10 11:08:41 -0400[diff] [blame]105CONFIG_DM_REGULATOR_TPS62360=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]106CONFIG_RAM=y
107CONFIG_SPL_RAM=y
108CONFIG_K3_SYSTEM_CONTROLLER=y
Lokesh Vutla247418b2019-06-07 19:25:59 +0530[diff] [blame]109CONFIG_REMOTEPROC_TI_K3_ARM64=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]110CONFIG_DM_RESET=y
111CONFIG_RESET_TI_SCI=y
112CONFIG_DM_SERIAL=y
Vignesh Raghavendra040362f2020-02-04 11:09:58 +0530[diff] [blame]113CONFIG_SOC_TI=y
114CONFIG_SPI=y
115CONFIG_DM_SPI=y
116CONFIG_CADENCE_QSPI=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]117CONFIG_SYSRESET=y
Kever Yang525ea472019-04-02 20:41:25 +0800[diff] [blame]118CONFIG_SPL_SYSRESET=y
Andrew F. Davise47bba02019-04-12 12:54:47 -0400[diff] [blame]119CONFIG_SYSRESET_TI_SCI=y
120CONFIG_TIMER=y
121CONFIG_SPL_TIMER=y
122CONFIG_OMAP_TIMER=y
Andreas Dannenberg355f0632019-06-04 17:55:52 -0500[diff] [blame]123CONFIG_FS_FAT_MAX_CLUSTSIZE=16384