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git01.mediatek.com / filogic / uboot / 90e7e42a48c8cf80273ad921dccfad19c74c1a32 / . / cpu / sa1100 / cpu.c
blob: 370ea6cb96a482a84027388e7a42a72dc5549a32 [file] [log] [blame]
wdenk4a9cbbe2002-08-27 09:48:53 +0000[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 * CPU specific code
31 */
32
33#include <common.h>
34#include <command.h>
35
36int cpu_init (void)
37{
38 /*
39 * setup up stack if necessary
40 */
41#ifdef CONFIG_USE_IRQ
42 IRQ_STACK_START = _armboot_end +
43 CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
44 FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
45 _armboot_real_end = FIQ_STACK_START + 4;
46#else
47 _armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
48#endif
49 return (0);
50}
51
52int cleanup_before_linux (void)
53{
54 /*
55 * this function is called just before we call linux
56 * it prepares the processor for linux
57 *
58 * just disable everything that can disturb booting linux
59 */
60
61 unsigned long i;
62
63 disable_interrupts ();
64
65 /* turn off I-cache */
66 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
67 i &= ~0x1000;
68 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
69
70 /* flush I-cache */
71 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
72
73 return (0);
74}
75
76int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
77{
78 extern void reset_cpu (ulong addr);
79
80 printf ("resetting ...\n");
81
82 udelay (50000); /* wait 50 ms */
83 disable_interrupts ();
84 reset_cpu (0);
85
86 /*NOTREACHED*/
87 return (0);
88}
89
90/* taken from blob */
91void icache_enable (void)
92{
93 register u32 i;
94
95 /* read control register */
96 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
97
98 /* set i-cache */
99 i |= 0x1000;
100
101 /* write back to control register */
102 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
103}
104
105void icache_disable (void)
106{
107 register u32 i;
108
109 /* read control register */
110 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
111
112 /* clear i-cache */
113 i &= ~0x1000;
114
115 /* write back to control register */
116 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
117
118 /* flush i-cache */
119 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
120}
121
122int icache_status (void)
123{
124 register u32 i;
125
126 /* read control register */
127 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
128
129 /* return bit */
130 return (i & 0x1000);
131}
132
133/* we will never enable dcache, because we have to setup MMU first */
134void dcache_enable (void)
135{
136 return;
137}
138
139void dcache_disable (void)
140{
141 return;
142}
143
144int dcache_status (void)
145{
146 return 0; /* always off */
147}