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wdenk56f94be2002-11-05 16:35:14 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <mpc8xx.h>
27#ifdef CONFIG_KUP4K_LOGO
28 #include "s1d13706.h"
29#endif
30
31
32typedef struct
33{
34 volatile unsigned char *VmemAddr;
35 volatile unsigned char *RegAddr;
36}FB_INFO_S1D13xxx;
37
38/* ------------------------------------------------------------------------- */
39
40#if 0
41static long int dram_size (long int, long int *, long int);
42#endif
43
44#ifdef CONFIG_KUP4K_LOGO
45 void lcd_logo(bd_t *bd);
46#endif
47
48/* ------------------------------------------------------------------------- */
49
50#define _NOT_USED_ 0xFFFFFFFF
51
52const uint sdram_table[] =
53{
54 /*
55 * Single Read. (Offset 0 in UPMA RAM)
56 */
57 0x1F07FC04,
58 0xEEAEFC04,
59 0x11ADFC04,
60 0xEFBBBC00,
61 0x1FF77C47, /* last */
62
63 /*
64 * SDRAM Initialization (offset 5 in UPMA RAM)
65 *
66 * This is no UPM entry point. The following definition uses
67 * the remaining space to establish an initialization
68 * sequence, which is executed by a RUN command.
69 *
70 */
71 0x1FF77C35,
72 0xEFEABC34,
73 0x1FB57C35, /* last */
74
75 /*
76 * Burst Read. (Offset 8 in UPMA RAM)
77 */
78 0x1F07FC04,
79 0xEEAEFC04,
80 0x10ADFC04,
81 0xF0AFFC00,
82 0xF0AFFC00,
83 0xF1AFFC00,
84 0xEFBBBC00,
85 0x1FF77C47, /* last */
86 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
87 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
88
89 /*
90 * Single Write. (Offset 18 in UPMA RAM)
91 */
92 0x1F27FC04,
93 0xEEAEBC00,
94 0x01B93C04,
95 0x1FF77C47, /* last */
96 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
97
98 /*
99 * Burst Write. (Offset 20 in UPMA RAM)
100 */
101 0x1F07FC04,
102 0xEEAEBC00,
103 0x10AD7C00,
104 0xF0AFFC00,
105 0xF0AFFC00,
106 0xE1BBBC04,
107 0x1FF77C47, /* last */
108 _NOT_USED_,
109 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
110 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
111
112 /*
113 * Refresh (Offset 30 in UPMA RAM)
114 */
115 0x1FF5FC84,
116 0xFFFFFC04,
117 0xFFFFFC04,
118 0xFFFFFC04,
119 0xFFFFFC84,
120 0xFFFFFC07, /* last */
121 _NOT_USED_, _NOT_USED_,
122 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
123
124 /*
125 * Exception. (Offset 3c in UPMA RAM)
126 */
127 0x7FFFFC07, /* last */
128 _NOT_USED_, _NOT_USED_, _NOT_USED_,
129};
130
131/* ------------------------------------------------------------------------- */
132
133
134/*
135 * Check Board Identity:
136 */
137
138int checkboard (void)
139{
140
141 printf ("### No HW ID - assuming KUP4K-Color\n");
142 return (0);
143}
144
145/* ------------------------------------------------------------------------- */
146
147long int initdram (int board_type)
148{
149 volatile immap_t *immap = (immap_t *)CFG_IMMR;
150 volatile memctl8xx_t *memctl = &immap->im_memctl;
151 long int size_b0 = 0;
152 long int size_b1 = 0;
153 long int size_b2 = 0;
154
155 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
156
157 /*
158 * Preliminary prescaler for refresh (depends on number of
159 * banks): This value is selected for four cycles every 62.4 us
160 * with two SDRAM banks or four cycles every 31.2 us with one
161 * bank. It will be adjusted after memory sizing.
162 */
163 memctl->memc_mptpr = CFG_MPTPR;
164
165 memctl->memc_mar = 0x00000088;
166
167 /*
168 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
169 * preliminary addresses - these have to be modified after the
170 * SDRAM size has been determined.
171 */
172/* memctl->memc_or1 = CFG_OR1_PRELIM; */
173/* memctl->memc_br1 = CFG_BR1_PRELIM; */
174
175/* memctl->memc_or2 = CFG_OR2_PRELIM; */
176/* memctl->memc_br2 = CFG_BR2_PRELIM; */
177
178
179 memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
180
181 udelay(200);
182
183 /* perform SDRAM initializsation sequence */
184
185 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
186 udelay(1);
187 memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
188 udelay(1);
189 memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
190 udelay(1);
191
192 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
193 udelay(1);
194 memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
195 udelay(1);
196 memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
197 udelay(1);
198
199 memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
200 udelay(1);
201 memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
202 udelay(1);
203 memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
204 udelay(1);
205
206
207 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
208
209 udelay (1000);
210
211 size_b0 = 0x00800000;
212 size_b1 = 0x00800000;
213 size_b2 = 0x00800000;
214
215
216 memctl->memc_mptpr = CFG_MPTPR;
217 udelay(1000);
218
219 memctl->memc_or1 = 0xFF800A00;
220 memctl->memc_br1 = 0x00000081;
221
222 memctl->memc_or2 = 0xFF000A00;
223 memctl->memc_br2 = 0x00800081;
224
225 memctl->memc_or3 = 0xFE000A00;
226 memctl->memc_br3 = 0x01000081;
227
228 udelay(10000);
229
230
231 return (size_b0 + size_b1 + size_b2);
232}
233
234/* ------------------------------------------------------------------------- */
235
236/*
237 * Check memory range for valid RAM. A simple memory test determines
238 * the actually available RAM size between addresses `base' and
239 * `base + maxsize'. Some (not all) hardware errors are detected:
240 * - short between address lines
241 * - short between data lines
242 */
243#if 0
244static long int dram_size (long int mamr_value, long int *base, long int maxsize)
245{
246 volatile immap_t *immap = (immap_t *)CFG_IMMR;
247 volatile memctl8xx_t *memctl = &immap->im_memctl;
248 volatile long int *addr;
249 ulong cnt, val;
250 ulong save[32]; /* to make test non-destructive */
251 unsigned char i = 0;
252
253 memctl->memc_mamr = mamr_value;
254
255 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
256 addr = base + cnt; /* pointer arith! */
257
258 save[i++] = *addr;
259 *addr = ~cnt;
260 }
261
262 /* write 0 to base address */
263 addr = base;
264 save[i] = *addr;
265 *addr = 0;
266
267 /* check at base address */
268 if ((val = *addr) != 0) {
269 *addr = save[i];
270 return (0);
271 }
272
273 for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
274 addr = base + cnt; /* pointer arith! */
275
276 val = *addr;
277 *addr = save[--i];
278
279 if (val != (~cnt)) {
280 return (cnt * sizeof(long));
281 }
282 }
283 return (maxsize);
284}
285#endif
286
287int misc_init_r (void)
288{
289 DECLARE_GLOBAL_DATA_PTR;
290
wdenk90e7e422002-12-04 23:39:58 +0000291#ifdef CONFIG_STATUS_LED
292 volatile immap_t *immap = (immap_t *)CFG_IMMR;
293#endif
wdenk56f94be2002-11-05 16:35:14 +0000294#ifdef CONFIG_KUP4K_LOGO
295 bd_t *bd = gd->bd;
296
297
298 lcd_logo(bd);
299#endif /* CONFIG_KUP4K_LOGO */
wdenk90e7e422002-12-04 23:39:58 +0000300#ifdef CONFIG_IDE_LED
301 /* Configure PA8 as output port */
302 immap->im_ioport.iop_padir |= 0x80;
303 immap->im_ioport.iop_paodr |= 0x80;
304 immap->im_ioport.iop_papar &= ~0x80;
305 immap->im_ioport.iop_padat |= 0x80; /* turn it off */
306#endif
wdenk56f94be2002-11-05 16:35:14 +0000307 return(0);
308}
309
310#ifdef CONFIG_KUP4K_LOGO
311void lcd_logo(bd_t *bd){
312
313 FB_INFO_S1D13xxx fb_info;
314 S1D_INDEX s1dReg;
315 S1D_VALUE s1dValue;
316 volatile immap_t *immr = (immap_t *)CFG_IMMR;
317 volatile memctl8xx_t *memctl;
318 ushort i;
319 uchar *fb;
320 int rs, gs, bs;
321 int r = 8, g = 8, b = 4;
322 int r1,g1,b1;
323
324/*----------------------------------------------------------------------------- */
325/**/
326/* Initialize the chip and the frame buffer driver. */
327/**/
328/*----------------------------------------------------------------------------- */
329 memctl = &immr->im_memctl;
330/* memctl->memc_or5 = 0xFFC007F0; / * 4 MB 17 WS or externel TA */
331/* memctl->memc_br5 = 0x80000801; / * Start at 0x80000000 */
332
333 memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */
334 memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
335
336
337
338
339
340 fb_info.VmemAddr = (unsigned char*)(S1D_PHYSICAL_VMEM_ADDR);
341 fb_info.RegAddr = (unsigned char*)(S1D_PHYSICAL_REG_ADDR);
342
343 if ((((S1D_VALUE*)fb_info.RegAddr)[0] != 0x28) || (((S1D_VALUE*)fb_info.RegAddr)[1] != 0x14))
344 {
345 printf("Warning:LCD Controller S1D13706 not found\n");
346 return;
347 }
348
349 /* init controller */
350 for (i = 0; i < sizeof(aS1DRegs)/sizeof(aS1DRegs[0]); i++)
351 {
352 s1dReg = aS1DRegs[i].Index;
353 s1dValue = aS1DRegs[i].Value;
354/* printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
355 ((S1D_VALUE*)fb_info.RegAddr)[s1dReg/sizeof(S1D_VALUE)] = s1dValue;
356 }
357
358#undef MONOCHROME
359#ifdef MONOCHROME
360 switch(bd->bi_busfreq){
361#if 0
362 case 24000000:
363 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
364 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x28;
365 break;
366 case 32000000:
367 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
368 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x33;
369 break;
370#endif
371 case 40000000:
372 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
373 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x40;
374 break;
375 case 48000000:
376 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
377 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x4C;
378 break;
379 default:
380 printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
381 case 64000000:
382 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
383 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x69;
384 break;
385 }
386 ((S1D_VALUE*)fb_info.RegAddr)[0x10] = 0x00;
387#else
388 switch(bd->bi_busfreq){
389#if 0
390 case 24000000:
391 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
392 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
393 break;
394 case 32000000:
395 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
396 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
397 break;
398#endif
399 case 40000000:
400 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
401 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x41;
402 break;
403 case 48000000:
404 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
405 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
406 break;
407 default:
408 printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
409 case 64000000:
410 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
411 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x66;
412 break;
413 }
414#endif
415
416
417 /* create and set colormap */
418 rs = 256 / (r - 1);
419 gs = 256 / (g - 1);
420 bs = 256 / (b - 1);
421 for(i=0;i<256;i++){
422 r1=(rs * ((i / (g * b)) % r)) * 255;
423 g1=(gs * ((i / b) % g)) * 255;
424 b1=(bs * ((i) % b)) * 255;
425/* printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
426 S1D_WRITE_PALETTE(fb_info.RegAddr,i,(r1>>4),(g1>>4),(b1>>4));
427 }
428
429 /* copy bitmap */
430 fb = (char *) (fb_info.VmemAddr);
431 memcpy (fb, (uchar *)CONFIG_KUP4K_LOGO, 320 * 240);
432}
433#endif /* CONFIG_KUP4K_LOGO */
434
wdenk90e7e422002-12-04 23:39:58 +0000435#ifdef CONFIG_IDE_LED
436void ide_led (uchar led, uchar status)
437{
438 volatile immap_t *immap = (immap_t *)CFG_IMMR;
439 /* We have one led for both pcmcia slots */
440 if (status) { /* led on */
441 immap->im_ioport.iop_padat &= ~0x80;
442 } else {
443 immap->im_ioport.iop_padat |= 0x80;
444 }
445}
446#endif