Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the SAMA5D3xEK board. |
| 4 | * |
| 5 | * Copyright (C) 2012 - 2013 Atmel |
| 6 | * |
| 7 | * based on at91sam9m10g45ek.h by: |
| 8 | * Stelian Pop <stelian@popies.net> |
| 9 | * Lead Tech Design <www.leadtechdesign.com> |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
Wu, Josh | 4258754 | 2015-03-30 14:51:19 +0800 | [diff] [blame] | 15 | #include "at91-sama5_common.h" |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 16 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 17 | /* |
| 18 | * This needs to be defined for the OHCI code to work but it is defined as |
| 19 | * ATMEL_ID_UHPHS in the CPU specific header files. |
| 20 | */ |
Wenyou Yang | d19b901 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 21 | #define ATMEL_ID_UHP 32 |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 22 | |
| 23 | /* |
| 24 | * Specify the clock enable bit in the PMC_SCER register. |
| 25 | */ |
Wenyou Yang | d19b901 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 26 | #define ATMEL_PMC_UHP (1 << 6) |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 27 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 28 | /* board specific (not enough SRAM) */ |
| 29 | #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 |
| 30 | |
Bo Shen | b15f4f6 | 2014-07-18 16:43:08 +0800 | [diff] [blame] | 31 | /* NOR flash */ |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 32 | #ifdef CONFIG_MTD_NOR_FLASH |
Bo Shen | b15f4f6 | 2014-07-18 16:43:08 +0800 | [diff] [blame] | 33 | #define CONFIG_SYS_FLASH_BASE 0x10000000 |
| 34 | #define CONFIG_SYS_MAX_FLASH_SECT 131 |
| 35 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
Bo Shen | b15f4f6 | 2014-07-18 16:43:08 +0800 | [diff] [blame] | 36 | #endif |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 37 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 38 | /* SDRAM */ |
Wenyou Yang | d19b901 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 39 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 40 | #define CONFIG_SYS_SDRAM_SIZE 0x20000000 |
| 41 | |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 42 | #ifdef CONFIG_SPL_BUILD |
Wenyou Yang | 9a0e91f | 2017-04-14 08:51:42 +0800 | [diff] [blame] | 43 | #define CONFIG_SYS_INIT_SP_ADDR 0x318000 |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 44 | #else |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 45 | #define CONFIG_SYS_INIT_SP_ADDR \ |
Wenyou Yang | 9a0e91f | 2017-04-14 08:51:42 +0800 | [diff] [blame] | 46 | (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 47 | #endif |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 48 | |
| 49 | /* SerialFlash */ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 50 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 51 | /* NAND flash */ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 52 | #ifdef CONFIG_CMD_NAND |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 53 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Wenyou Yang | d19b901 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 54 | #define CONFIG_SYS_NAND_BASE 0x60000000 |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 55 | /* our ALE is AD21 */ |
| 56 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 57 | /* our CLE is AD22 */ |
| 58 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
Tom Rini | 00448d2 | 2017-07-28 21:31:42 -0400 | [diff] [blame] | 59 | #endif |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 60 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 61 | /* USB */ |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 62 | #ifdef CONFIG_CMD_USB |
Bo Shen | 4a985df | 2013-10-21 16:14:00 +0800 | [diff] [blame] | 63 | #define CONFIG_USB_ATMEL_CLK_SEL_UPLL |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 64 | #define CONFIG_USB_OHCI_NEW |
| 65 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
| 66 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI |
| 67 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" |
| 68 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 69 | #endif |
| 70 | |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 71 | /* SPL */ |
Wenyou Yang | 9a0e91f | 2017-04-14 08:51:42 +0800 | [diff] [blame] | 72 | #define CONFIG_SPL_MAX_SIZE 0x18000 |
Bo Shen | f92b298 | 2013-11-15 11:12:38 +0800 | [diff] [blame] | 73 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
| 74 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 75 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
| 76 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
| 77 | |
Bo Shen | 37a36b3 | 2014-03-03 14:47:15 +0800 | [diff] [blame] | 78 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| 79 | |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 80 | #ifdef CONFIG_SD_BOOT |
Guillaume GARDET | 602a16c | 2014-10-15 17:53:11 +0200 | [diff] [blame] | 81 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 82 | #endif |
Bo Shen | 540c031 | 2014-03-03 14:47:17 +0800 | [diff] [blame] | 83 | |
Bo Shen | 60f3dd3 | 2013-05-12 22:40:54 +0000 | [diff] [blame] | 84 | #endif |