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Priyanka Jainfd45ca02018-11-28 13:04:27 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
Yangbo Lubb32e682021-06-03 10:51:19 +08003 * Copyright 2018-2021 NXP
Priyanka Jainfd45ca02018-11-28 13:04:27 +00004 */
5
6#ifndef __LX2_COMMON_H
7#define __LX2_COMMON_H
8
9#include <asm/arch/stream_id_lsch3.h>
10#include <asm/arch/config.h>
11#include <asm/arch/soc.h>
12
13#define CONFIG_REMAKE_ELF
Priyanka Jainfd45ca02018-11-28 13:04:27 +000014#define CONFIG_FSL_MEMAC
15
16#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
17#define CONFIG_SYS_FLASH_BASE 0x20000000
18
Priyanka Jainfd45ca02018-11-28 13:04:27 +000019/* DDR */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000020#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
21#define CONFIG_VERY_BIG_RAM
22#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
23#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
24#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
25#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
26#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
Priyanka Jainfd45ca02018-11-28 13:04:27 +000027#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
28#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
29#define SPD_EEPROM_ADDRESS1 0x51
30#define SPD_EEPROM_ADDRESS2 0x52
31#define SPD_EEPROM_ADDRESS3 0x53
32#define SPD_EEPROM_ADDRESS4 0x54
33#define SPD_EEPROM_ADDRESS5 0x55
34#define SPD_EEPROM_ADDRESS6 0x56
35#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
36#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
37#define CONFIG_DIMM_SLOTS_PER_CTLR 2
38#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Priyanka Jainfd45ca02018-11-28 13:04:27 +000039#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
40
41/* Miscellaneous configurable options */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000042
43/* SMP Definitinos */
Michael Wallef056e0f2020-06-01 21:53:26 +020044#define CPU_RELEASE_ADDR secondary_boot_addr
Priyanka Jainfd45ca02018-11-28 13:04:27 +000045
46/* Generic Timer Definitions */
47/*
48 * This is not an accurate number. It is used in start.S. The frequency
49 * will be udpated later when get_bus_freq(0) is available.
50 */
51
52#define COUNTER_FREQUENCY 25000000 /* 25MHz */
53
Priyanka Jainfd45ca02018-11-28 13:04:27 +000054/* Serial Port */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000055#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
56#define CONFIG_SYS_SERIAL0 0x21c0000
57#define CONFIG_SYS_SERIAL1 0x21d0000
58#define CONFIG_SYS_SERIAL2 0x21e0000
59#define CONFIG_SYS_SERIAL3 0x21f0000
60/*below might needs to be removed*/
61#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
62 (void *)CONFIG_SYS_SERIAL1, \
63 (void *)CONFIG_SYS_SERIAL2, \
64 (void *)CONFIG_SYS_SERIAL3 }
Priyanka Jainfd45ca02018-11-28 13:04:27 +000065
66/* MC firmware */
67#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
68#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
69#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
70#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
71#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
72
73/* Define phy_reset function to boot the MC based on mcinitcmd.
74 * This happens late enough to properly fixup u-boot env MAC addresses.
75 */
76#define CONFIG_RESET_PHY_R
77
78/*
79 * Carve out a DDR region which will not be used by u-boot/Linux
80 *
81 * It will be used by MC and Debug Server. The MC region must be
82 * 512MB aligned, so the min size to hide is 512MB.
83 */
84#ifdef CONFIG_FSL_MC_ENET
Meenakshi Aggarwal67f195c2019-02-27 14:41:02 +053085#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
Priyanka Jainfd45ca02018-11-28 13:04:27 +000086#endif
87
88/* I2C bus multiplexer */
89#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
90#define I2C_MUX_CH_DEFAULT 0x8
91
92/* RTC */
93#define RTC
94#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
95
96/* EEPROM */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000097#define CONFIG_SYS_I2C_EEPROM_NXID
98#define CONFIG_SYS_EEPROM_BUS_NUM 0
Priyanka Jainfd45ca02018-11-28 13:04:27 +000099
100/* Qixis */
101#define CONFIG_FSL_QIXIS
102#define CONFIG_QIXIS_I2C_ACCESS
103#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
104
105/* PCI */
106#ifdef CONFIG_PCI
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000107#define CONFIG_PCI_SCAN_SHOW
108#endif
109
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000110/* SATA */
111
112#ifdef CONFIG_SCSI
113#define CONFIG_SCSI_AHCI_PLAT
114#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
115#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
116#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
117#define CONFIG_SYS_SCSI_MAX_LUN 1
118#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
119 CONFIG_SYS_SCSI_MAX_LUN)
120#endif
121
122/* USB */
Tom Rini8a091622021-07-09 10:11:55 -0400123#ifdef CONFIG_USB_HOST
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +0530124#ifndef CONFIG_TARGET_LX2162AQDS
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000125#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
126#endif
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +0530127#endif
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000128
Tom Rini8c70baa2021-12-14 13:36:40 -0500129#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000130
131#define CONFIG_HWCONFIG
132#define HWCONFIG_BUFFER_SIZE 128
133
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000134/* Monitor Command Prompt */
135#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
136#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
137 sizeof(CONFIG_SYS_PROMPT) + 16)
138#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000139#define CONFIG_SYS_MAXARGS 64 /* max command args */
140
141#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
142
143/* Initial environment variables */
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530144#define XSPI_MC_INIT_CMD \
145 "sf probe 0:0 && " \
146 "sf read 0x80640000 0x640000 0x80000 && " \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530147 "sf read $fdt_addr_r 0xf00000 0x100000 && " \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530148 "env exists secureboot && " \
149 "esbc_validate 0x80640000 && " \
150 "esbc_validate 0x80680000; " \
151 "sf read 0x80a00000 0xa00000 0x300000 && " \
152 "sf read 0x80e00000 0xe00000 0x100000; " \
153 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000154
155#define SD_MC_INIT_CMD \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000156 "mmc read 0x80a00000 0x5000 0x1200;" \
157 "mmc read 0x80e00000 0x7000 0x800;" \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530158 "mmc read $fdt_addr_r 0x7800 0x800;" \
Udit Agarwalf34581e2018-12-14 04:43:32 +0000159 "env exists secureboot && " \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000160 "mmc read 0x80640000 0x3200 0x20 && " \
161 "mmc read 0x80680000 0x3400 0x20 && " \
162 "esbc_validate 0x80640000 && " \
163 "esbc_validate 0x80680000 ;" \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000164 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000165
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530166#define SD2_MC_INIT_CMD \
167 "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
168 "mmc read 0x80e00000 0x7000 0x800;" \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530169 "mmc read $fdt_addr_r 0x7800 0x800;" \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530170 "env exists secureboot && " \
171 "mmc read 0x80640000 0x3200 0x20 && " \
172 "mmc read 0x80680000 0x3400 0x20 && " \
173 "esbc_validate 0x80640000 && " \
174 "esbc_validate 0x80680000 ;" \
175 "fsl_mc start mc 0x80a00000 0x80e00000\0"
176
Priyanka Jain16744062019-01-24 05:22:18 +0000177#define EXTRA_ENV_SETTINGS \
178 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
179 "ramdisk_addr=0x800000\0" \
180 "ramdisk_size=0x2000000\0" \
181 "fdt_high=0xa0000000\0" \
182 "initrd_high=0xffffffffffffffff\0" \
183 "fdt_addr=0x64f00000\0" \
184 "kernel_start=0x1000000\0" \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000185 "kernelheader_start=0x600000\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000186 "scriptaddr=0x80000000\0" \
187 "scripthdraddr=0x80080000\0" \
188 "fdtheader_addr_r=0x80100000\0" \
189 "kernelheader_addr_r=0x80200000\0" \
190 "kernel_addr_r=0x81000000\0" \
191 "kernelheader_size=0x40000\0" \
192 "fdt_addr_r=0x90000000\0" \
193 "load_addr=0xa0000000\0" \
194 "kernel_size=0x2800000\0" \
195 "kernel_addr_sd=0x8000\0" \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000196 "kernelhdr_addr_sd=0x3000\0" \
Manish Tomarebef67f2020-11-05 14:08:56 +0530197 "kernel_size_sd=0x14000\0" \
Udit Agarwal11e1a572019-11-20 08:49:06 +0000198 "kernelhdr_size_sd=0x20\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000199 "console=ttyAMA0,38400n8\0" \
200 BOOTENV \
201 "mcmemsize=0x70000000\0" \
202 XSPI_MC_INIT_CMD \
Priyanka Jain16744062019-01-24 05:22:18 +0000203 "scan_dev_for_boot_part=" \
204 "part list ${devtype} ${devnum} devplist; " \
205 "env exists devplist || setenv devplist 1; " \
206 "for distro_bootpart in ${devplist}; do " \
207 "if fstype ${devtype} " \
208 "${devnum}:${distro_bootpart} " \
209 "bootfstype; then " \
210 "run scan_dev_for_boot; " \
211 "fi; " \
212 "done\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000213 "boot_a_script=" \
214 "load ${devtype} ${devnum}:${distro_bootpart} " \
215 "${scriptaddr} ${prefix}${script}; " \
216 "env exists secureboot && load ${devtype} " \
217 "${devnum}:${distro_bootpart} " \
218 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
219 "&& esbc_validate ${scripthdraddr};" \
220 "source ${scriptaddr}\0"
221
222#define XSPI_NOR_BOOTCOMMAND \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530223 "sf probe 0:0; " \
224 "sf read 0x806c0000 0x6c0000 0x40000; " \
225 "env exists mcinitcmd && env exists secureboot" \
226 " && esbc_validate 0x806c0000; " \
227 "sf read 0x80d00000 0xd00000 0x100000; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000228 "env exists mcinitcmd && " \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530229 "fsl_mc lazyapply dpl 0x80d00000; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000230 "run distro_bootcmd;run xspi_bootcmd; " \
231 "env exists secureboot && esbc_halt;"
232
233#define SD_BOOTCOMMAND \
234 "env exists mcinitcmd && mmcinfo; " \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000235 "mmc read 0x80d00000 0x6800 0x800; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000236 "env exists mcinitcmd && env exists secureboot " \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000237 " && mmc read 0x806C0000 0x3600 0x20 " \
238 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000239 "&& fsl_mc lazyapply dpl 0x80d00000;" \
Priyanka Jain16744062019-01-24 05:22:18 +0000240 "run distro_bootcmd;run sd_bootcmd;" \
241 "env exists secureboot && esbc_halt;"
242
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530243#define SD2_BOOTCOMMAND \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530244 "mmc dev 1; env exists mcinitcmd && mmcinfo; " \
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530245 "mmc read 0x80d00000 0x6800 0x800; " \
246 "env exists mcinitcmd && env exists secureboot " \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530247 " && mmc read 0x806C0000 0x3600 0x20 " \
248 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530249 "&& fsl_mc lazyapply dpl 0x80d00000;" \
250 "run distro_bootcmd;run sd2_bootcmd;" \
251 "env exists secureboot && esbc_halt;"
252
Priyanka Jain16744062019-01-24 05:22:18 +0000253#define BOOT_TARGET_DEVICES(func) \
254 func(USB, usb, 0) \
255 func(MMC, mmc, 0) \
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530256 func(MMC, mmc, 1) \
Meenakshi Aggarwal26224642020-03-11 20:51:47 +0530257 func(SCSI, scsi, 0) \
258 func(DHCP, dhcp, na)
Priyanka Jain16744062019-01-24 05:22:18 +0000259#include <config_distro_bootcmd.h>
260
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000261#endif /* __LX2_COMMON_H */