Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 2 | /* |
| 3 | * am335x_sl50.h |
| 4 | * |
| 5 | * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_AM335X_EVM_H |
| 9 | #define __CONFIG_AM335X_EVM_H |
| 10 | |
| 11 | #include <configs/ti_am335x_common.h> |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 12 | |
| 13 | #ifndef CONFIG_SPL_BUILD |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 14 | # define CONFIG_TIMESTAMP |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 15 | #endif |
| 16 | |
| 17 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) |
| 18 | |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 19 | /* Clock Defines */ |
| 20 | #define V_OSCK 24000000 /* Clock output from T2 */ |
| 21 | #define V_SCLK (V_OSCK) |
| 22 | |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 23 | #ifndef CONFIG_SPL_BUILD |
| 24 | |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 25 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 26 | "scriptaddr=0x80000000\0" \ |
| 27 | "pxefile_addr_r=0x80100000\0" \ |
| 28 | "kernel_addr_r=0x82000000\0" \ |
| 29 | "fdt_addr_r=0x88000000\0" \ |
| 30 | "ramdisk_addr_r=0x88080000\0" \ |
| 31 | |
| 32 | #define BOOT_TARGET_DEVICES(func) \ |
| 33 | func(MMC, mmc, 0) \ |
| 34 | func(MMC, mmc, 1) |
| 35 | |
| 36 | #define AM335XX_BOARD_FDTFILE \ |
| 37 | "fdtfile=am335x-sl50.dtb\0" \ |
| 38 | |
| 39 | #include <config_distro_bootcmd.h> |
| 40 | |
| 41 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 42 | AM335XX_BOARD_FDTFILE \ |
| 43 | MEM_LAYOUT_ENV_SETTINGS \ |
| 44 | BOOTENV |
| 45 | |
| 46 | #endif |
| 47 | |
| 48 | /* NS16550 Configuration */ |
| 49 | #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ |
| 50 | #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ |
| 51 | #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ |
| 52 | #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ |
| 53 | #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ |
| 54 | #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 55 | |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 56 | /* PMIC support */ |
| 57 | #define CONFIG_POWER_TPS65217 |
| 58 | #define CONFIG_POWER_TPS65910 |
| 59 | |
| 60 | /* SPL */ |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 61 | |
| 62 | /* Bootcount using the RTC block */ |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 63 | #define CONFIG_SYS_BOOTCOUNT_BE |
| 64 | |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 65 | /* Network. */ |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 66 | |
| 67 | #endif /* ! __CONFIG_AM335X_SL50_H */ |