Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2016 |
| 4 | * Author: Amit Singh Tomar, amittomer25@gmail.com |
| 5 | * |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 6 | * Ethernet driver for H3/A64/A83T based SoC's |
| 7 | * |
| 8 | * It is derived from the work done by |
| 9 | * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS! |
| 10 | * |
| 11 | */ |
| 12 | |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 13 | #include <cpu_func.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 14 | #include <log.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 15 | #include <asm/cache.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 16 | #include <asm/global_data.h> |
Samuel Holland | 06feb81 | 2021-09-11 16:50:47 -0500 | [diff] [blame] | 17 | #include <asm/gpio.h> |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 18 | #include <asm/io.h> |
| 19 | #include <asm/arch/clock.h> |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 20 | #include <common.h> |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 21 | #include <clk.h> |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 22 | #include <dm.h> |
| 23 | #include <fdt_support.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 24 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 25 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 26 | #include <linux/delay.h> |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 27 | #include <linux/err.h> |
| 28 | #include <malloc.h> |
| 29 | #include <miiphy.h> |
| 30 | #include <net.h> |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 31 | #include <reset.h> |
Andre Przywara | 26e549b | 2018-04-04 01:31:15 +0100 | [diff] [blame] | 32 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 33 | #include <wait_bit.h> |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 34 | |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 35 | #define MDIO_CMD_MII_BUSY BIT(0) |
| 36 | #define MDIO_CMD_MII_WRITE BIT(1) |
| 37 | |
| 38 | #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0 |
| 39 | #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4 |
| 40 | #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000 |
| 41 | #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12 |
Andre Przywara | b41f247 | 2020-07-06 01:40:45 +0100 | [diff] [blame] | 42 | #define MDIO_CMD_MII_CLK_CSR_DIV_16 0x0 |
| 43 | #define MDIO_CMD_MII_CLK_CSR_DIV_32 0x1 |
| 44 | #define MDIO_CMD_MII_CLK_CSR_DIV_64 0x2 |
| 45 | #define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3 |
| 46 | #define MDIO_CMD_MII_CLK_CSR_SHIFT 20 |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 47 | |
| 48 | #define CONFIG_TX_DESCR_NUM 32 |
| 49 | #define CONFIG_RX_DESCR_NUM 32 |
Hans de Goede | fcdb3b3 | 2016-07-27 17:31:17 +0200 | [diff] [blame] | 50 | #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */ |
| 51 | |
| 52 | /* |
| 53 | * The datasheet says that each descriptor can transfers up to 4096 bytes |
| 54 | * But later, the register documentation reduces that value to 2048, |
| 55 | * using 2048 cause strange behaviours and even BSP driver use 2047 |
| 56 | */ |
| 57 | #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */ |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 58 | |
| 59 | #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) |
| 60 | #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) |
| 61 | |
| 62 | #define H3_EPHY_DEFAULT_VALUE 0x58000 |
| 63 | #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15) |
| 64 | #define H3_EPHY_ADDR_SHIFT 20 |
| 65 | #define REG_PHY_ADDR_MASK GENMASK(4, 0) |
| 66 | #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ |
| 67 | #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ |
| 68 | #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ |
| 69 | |
| 70 | #define SC_RMII_EN BIT(13) |
| 71 | #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */ |
| 72 | #define SC_ETCS_MASK GENMASK(1, 0) |
| 73 | #define SC_ETCS_EXT_GMII 0x1 |
| 74 | #define SC_ETCS_INT_GMII 0x2 |
Icenowy Zheng | 525dc44 | 2018-11-23 00:37:48 +0100 | [diff] [blame] | 75 | #define SC_ETXDC_MASK GENMASK(12, 10) |
| 76 | #define SC_ETXDC_OFFSET 10 |
| 77 | #define SC_ERXDC_MASK GENMASK(9, 5) |
| 78 | #define SC_ERXDC_OFFSET 5 |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 79 | |
| 80 | #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) |
| 81 | |
| 82 | #define AHB_GATE_OFFSET_EPHY 0 |
| 83 | |
Lothar Felten | acb9a5b | 2018-07-13 10:45:27 +0200 | [diff] [blame] | 84 | /* IO mux settings */ |
| 85 | #define SUN8I_IOMUX_H3 2 |
Andre Przywara | 882a923 | 2021-01-11 21:11:49 +0100 | [diff] [blame] | 86 | #define SUN8I_IOMUX_R40 5 |
| 87 | #define SUN8I_IOMUX_H6 5 |
| 88 | #define SUN8I_IOMUX_H616 2 |
Lothar Felten | acb9a5b | 2018-07-13 10:45:27 +0200 | [diff] [blame] | 89 | #define SUN8I_IOMUX 4 |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 90 | |
| 91 | /* H3/A64 EMAC Register's offset */ |
| 92 | #define EMAC_CTL0 0x00 |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 93 | #define EMAC_CTL0_FULL_DUPLEX BIT(0) |
| 94 | #define EMAC_CTL0_SPEED_MASK GENMASK(3, 2) |
| 95 | #define EMAC_CTL0_SPEED_10 (0x2 << 2) |
| 96 | #define EMAC_CTL0_SPEED_100 (0x3 << 2) |
| 97 | #define EMAC_CTL0_SPEED_1000 (0x0 << 2) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 98 | #define EMAC_CTL1 0x04 |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 99 | #define EMAC_CTL1_SOFT_RST BIT(0) |
| 100 | #define EMAC_CTL1_BURST_LEN_SHIFT 24 |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 101 | #define EMAC_INT_STA 0x08 |
| 102 | #define EMAC_INT_EN 0x0c |
| 103 | #define EMAC_TX_CTL0 0x10 |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 104 | #define EMAC_TX_CTL0_TX_EN BIT(31) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 105 | #define EMAC_TX_CTL1 0x14 |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 106 | #define EMAC_TX_CTL1_TX_MD BIT(1) |
| 107 | #define EMAC_TX_CTL1_TX_DMA_EN BIT(30) |
| 108 | #define EMAC_TX_CTL1_TX_DMA_START BIT(31) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 109 | #define EMAC_TX_FLOW_CTL 0x1c |
| 110 | #define EMAC_TX_DMA_DESC 0x20 |
| 111 | #define EMAC_RX_CTL0 0x24 |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 112 | #define EMAC_RX_CTL0_RX_EN BIT(31) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 113 | #define EMAC_RX_CTL1 0x28 |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 114 | #define EMAC_RX_CTL1_RX_MD BIT(1) |
Andre Przywara | 5942282 | 2020-07-06 01:40:43 +0100 | [diff] [blame] | 115 | #define EMAC_RX_CTL1_RX_RUNT_FRM BIT(2) |
| 116 | #define EMAC_RX_CTL1_RX_ERR_FRM BIT(3) |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 117 | #define EMAC_RX_CTL1_RX_DMA_EN BIT(30) |
| 118 | #define EMAC_RX_CTL1_RX_DMA_START BIT(31) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 119 | #define EMAC_RX_DMA_DESC 0x34 |
| 120 | #define EMAC_MII_CMD 0x48 |
| 121 | #define EMAC_MII_DATA 0x4c |
| 122 | #define EMAC_ADDR0_HIGH 0x50 |
| 123 | #define EMAC_ADDR0_LOW 0x54 |
| 124 | #define EMAC_TX_DMA_STA 0xb0 |
| 125 | #define EMAC_TX_CUR_DESC 0xb4 |
| 126 | #define EMAC_TX_CUR_BUF 0xb8 |
| 127 | #define EMAC_RX_DMA_STA 0xc0 |
| 128 | #define EMAC_RX_CUR_DESC 0xc4 |
| 129 | |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 130 | #define EMAC_DESC_OWN_DMA BIT(31) |
| 131 | #define EMAC_DESC_LAST_DESC BIT(30) |
| 132 | #define EMAC_DESC_FIRST_DESC BIT(29) |
| 133 | #define EMAC_DESC_CHAIN_SECOND BIT(24) |
| 134 | |
Andre Przywara | 5942282 | 2020-07-06 01:40:43 +0100 | [diff] [blame] | 135 | #define EMAC_DESC_RX_ERROR_MASK 0x400068db |
| 136 | |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 137 | DECLARE_GLOBAL_DATA_PTR; |
| 138 | |
| 139 | enum emac_variant { |
| 140 | A83T_EMAC = 1, |
| 141 | H3_EMAC, |
| 142 | A64_EMAC, |
Lothar Felten | e8cbced | 2018-07-13 10:45:28 +0200 | [diff] [blame] | 143 | R40_GMAC, |
Samuel Holland | 3386e9a | 2020-05-07 18:10:51 -0500 | [diff] [blame] | 144 | H6_EMAC, |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 145 | }; |
| 146 | |
| 147 | struct emac_dma_desc { |
| 148 | u32 status; |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 149 | u32 ctl_size; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 150 | u32 buf_addr; |
| 151 | u32 next; |
| 152 | } __aligned(ARCH_DMA_MINALIGN); |
| 153 | |
| 154 | struct emac_eth_dev { |
| 155 | struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM]; |
| 156 | struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM]; |
| 157 | char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); |
| 158 | char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); |
| 159 | |
| 160 | u32 interface; |
| 161 | u32 phyaddr; |
| 162 | u32 link; |
| 163 | u32 speed; |
| 164 | u32 duplex; |
| 165 | u32 phy_configured; |
| 166 | u32 tx_currdescnum; |
| 167 | u32 rx_currdescnum; |
| 168 | u32 addr; |
| 169 | u32 tx_slot; |
| 170 | bool use_internal_phy; |
| 171 | |
| 172 | enum emac_variant variant; |
| 173 | void *mac_reg; |
| 174 | phys_addr_t sysctl_reg; |
| 175 | struct phy_device *phydev; |
| 176 | struct mii_dev *bus; |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 177 | struct clk tx_clk; |
Jagan Teki | 727ed79 | 2019-02-28 00:27:00 +0530 | [diff] [blame] | 178 | struct clk ephy_clk; |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 179 | struct reset_ctl tx_rst; |
Jagan Teki | 727ed79 | 2019-02-28 00:27:00 +0530 | [diff] [blame] | 180 | struct reset_ctl ephy_rst; |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 181 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 182 | struct gpio_desc reset_gpio; |
| 183 | #endif |
| 184 | }; |
| 185 | |
| 186 | |
| 187 | struct sun8i_eth_pdata { |
| 188 | struct eth_pdata eth_pdata; |
| 189 | u32 reset_delays[3]; |
Icenowy Zheng | 525dc44 | 2018-11-23 00:37:48 +0100 | [diff] [blame] | 190 | int tx_delay_ps; |
| 191 | int rx_delay_ps; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 192 | }; |
| 193 | |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 194 | |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 195 | static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
| 196 | { |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 197 | struct udevice *dev = bus->priv; |
| 198 | struct emac_eth_dev *priv = dev_get_priv(dev); |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 199 | u32 mii_cmd; |
| 200 | int ret; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 201 | |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 202 | mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 203 | MDIO_CMD_MII_PHY_REG_ADDR_MASK; |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 204 | mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 205 | MDIO_CMD_MII_PHY_ADDR_MASK; |
| 206 | |
Andre Przywara | b41f247 | 2020-07-06 01:40:45 +0100 | [diff] [blame] | 207 | /* |
| 208 | * The EMAC clock is either 200 or 300 MHz, so we need a divider |
| 209 | * of 128 to get the MDIO frequency below the required 2.5 MHz. |
| 210 | */ |
Heinrich Schuchardt | 6ffc023 | 2021-06-03 07:52:41 +0000 | [diff] [blame] | 211 | if (!priv->use_internal_phy) |
| 212 | mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << |
| 213 | MDIO_CMD_MII_CLK_CSR_SHIFT; |
Andre Przywara | b41f247 | 2020-07-06 01:40:45 +0100 | [diff] [blame] | 214 | |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 215 | mii_cmd |= MDIO_CMD_MII_BUSY; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 216 | |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 217 | writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 218 | |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 219 | ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD, |
| 220 | MDIO_CMD_MII_BUSY, false, |
| 221 | CONFIG_MDIO_TIMEOUT, true); |
| 222 | if (ret < 0) |
| 223 | return ret; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 224 | |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 225 | return readl(priv->mac_reg + EMAC_MII_DATA); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, |
| 229 | u16 val) |
| 230 | { |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 231 | struct udevice *dev = bus->priv; |
| 232 | struct emac_eth_dev *priv = dev_get_priv(dev); |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 233 | u32 mii_cmd; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 234 | |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 235 | mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 236 | MDIO_CMD_MII_PHY_REG_ADDR_MASK; |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 237 | mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 238 | MDIO_CMD_MII_PHY_ADDR_MASK; |
| 239 | |
Andre Przywara | b41f247 | 2020-07-06 01:40:45 +0100 | [diff] [blame] | 240 | /* |
| 241 | * The EMAC clock is either 200 or 300 MHz, so we need a divider |
| 242 | * of 128 to get the MDIO frequency below the required 2.5 MHz. |
| 243 | */ |
Heinrich Schuchardt | 6ffc023 | 2021-06-03 07:52:41 +0000 | [diff] [blame] | 244 | if (!priv->use_internal_phy) |
| 245 | mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << |
| 246 | MDIO_CMD_MII_CLK_CSR_SHIFT; |
Andre Przywara | b41f247 | 2020-07-06 01:40:45 +0100 | [diff] [blame] | 247 | |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 248 | mii_cmd |= MDIO_CMD_MII_WRITE; |
| 249 | mii_cmd |= MDIO_CMD_MII_BUSY; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 250 | |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 251 | writel(val, priv->mac_reg + EMAC_MII_DATA); |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 252 | writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 253 | |
Andre Przywara | 0dd619b | 2020-07-06 01:40:34 +0100 | [diff] [blame] | 254 | return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD, |
| 255 | MDIO_CMD_MII_BUSY, false, |
| 256 | CONFIG_MDIO_TIMEOUT, true); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 257 | } |
| 258 | |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 259 | static int sun8i_eth_write_hwaddr(struct udevice *dev) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 260 | { |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 261 | struct emac_eth_dev *priv = dev_get_priv(dev); |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 262 | struct eth_pdata *pdata = dev_get_plat(dev); |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 263 | uchar *mac_id = pdata->enetaddr; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 264 | u32 macid_lo, macid_hi; |
| 265 | |
| 266 | macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + |
| 267 | (mac_id[3] << 24); |
| 268 | macid_hi = mac_id[4] + (mac_id[5] << 8); |
| 269 | |
| 270 | writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH); |
| 271 | writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW); |
| 272 | |
| 273 | return 0; |
| 274 | } |
| 275 | |
| 276 | static void sun8i_adjust_link(struct emac_eth_dev *priv, |
| 277 | struct phy_device *phydev) |
| 278 | { |
| 279 | u32 v; |
| 280 | |
| 281 | v = readl(priv->mac_reg + EMAC_CTL0); |
| 282 | |
| 283 | if (phydev->duplex) |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 284 | v |= EMAC_CTL0_FULL_DUPLEX; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 285 | else |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 286 | v &= ~EMAC_CTL0_FULL_DUPLEX; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 287 | |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 288 | v &= ~EMAC_CTL0_SPEED_MASK; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 289 | |
| 290 | switch (phydev->speed) { |
| 291 | case 1000: |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 292 | v |= EMAC_CTL0_SPEED_1000; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 293 | break; |
| 294 | case 100: |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 295 | v |= EMAC_CTL0_SPEED_100; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 296 | break; |
| 297 | case 10: |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 298 | v |= EMAC_CTL0_SPEED_10; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 299 | break; |
| 300 | } |
| 301 | writel(v, priv->mac_reg + EMAC_CTL0); |
| 302 | } |
| 303 | |
Andre Przywara | 15651d8 | 2021-01-11 21:11:45 +0100 | [diff] [blame] | 304 | static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 305 | { |
| 306 | if (priv->use_internal_phy) { |
| 307 | /* H3 based SoC's that has an Internal 100MBit PHY |
| 308 | * needs to be configured and powered up before use |
| 309 | */ |
Andre Przywara | 15651d8 | 2021-01-11 21:11:45 +0100 | [diff] [blame] | 310 | reg &= ~H3_EPHY_DEFAULT_MASK; |
| 311 | reg |= H3_EPHY_DEFAULT_VALUE; |
| 312 | reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT; |
| 313 | reg &= ~H3_EPHY_SHUTDOWN; |
| 314 | return reg | H3_EPHY_SELECT; |
| 315 | } |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 316 | |
Andre Przywara | 15651d8 | 2021-01-11 21:11:45 +0100 | [diff] [blame] | 317 | /* This is to select External Gigabit PHY on those boards with |
| 318 | * an internal PHY. Does not hurt on other SoCs. Linux does |
| 319 | * it as well. |
| 320 | */ |
| 321 | return reg & ~H3_EPHY_SELECT; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 322 | } |
| 323 | |
Icenowy Zheng | 525dc44 | 2018-11-23 00:37:48 +0100 | [diff] [blame] | 324 | static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, |
| 325 | struct emac_eth_dev *priv) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 326 | { |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 327 | u32 reg; |
| 328 | |
Jagan Teki | 1cfc64c | 2019-02-28 00:26:51 +0530 | [diff] [blame] | 329 | if (priv->variant == R40_GMAC) { |
| 330 | /* Select RGMII for R40 */ |
| 331 | reg = readl(priv->sysctl_reg + 0x164); |
Samuel Holland | 97f2cf1 | 2020-05-07 18:10:50 -0500 | [diff] [blame] | 332 | reg |= SC_ETCS_INT_GMII | |
| 333 | SC_EPIT | |
| 334 | (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 335 | |
Jagan Teki | 1cfc64c | 2019-02-28 00:26:51 +0530 | [diff] [blame] | 336 | writel(reg, priv->sysctl_reg + 0x164); |
Lothar Felten | e8cbced | 2018-07-13 10:45:28 +0200 | [diff] [blame] | 337 | return 0; |
Jagan Teki | 1cfc64c | 2019-02-28 00:26:51 +0530 | [diff] [blame] | 338 | } |
| 339 | |
| 340 | reg = readl(priv->sysctl_reg + 0x30); |
Lothar Felten | e8cbced | 2018-07-13 10:45:28 +0200 | [diff] [blame] | 341 | |
Andre Przywara | 15651d8 | 2021-01-11 21:11:45 +0100 | [diff] [blame] | 342 | reg = sun8i_emac_set_syscon_ephy(priv, reg); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 343 | |
| 344 | reg &= ~(SC_ETCS_MASK | SC_EPIT); |
Samuel Holland | 3386e9a | 2020-05-07 18:10:51 -0500 | [diff] [blame] | 345 | if (priv->variant == H3_EMAC || |
| 346 | priv->variant == A64_EMAC || |
| 347 | priv->variant == H6_EMAC) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 348 | reg &= ~SC_RMII_EN; |
| 349 | |
| 350 | switch (priv->interface) { |
| 351 | case PHY_INTERFACE_MODE_MII: |
| 352 | /* default */ |
| 353 | break; |
| 354 | case PHY_INTERFACE_MODE_RGMII: |
Andre Przywara | 43bb158 | 2020-11-14 17:37:46 +0000 | [diff] [blame] | 355 | case PHY_INTERFACE_MODE_RGMII_ID: |
| 356 | case PHY_INTERFACE_MODE_RGMII_RXID: |
| 357 | case PHY_INTERFACE_MODE_RGMII_TXID: |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 358 | reg |= SC_EPIT | SC_ETCS_INT_GMII; |
| 359 | break; |
| 360 | case PHY_INTERFACE_MODE_RMII: |
| 361 | if (priv->variant == H3_EMAC || |
Samuel Holland | 3386e9a | 2020-05-07 18:10:51 -0500 | [diff] [blame] | 362 | priv->variant == A64_EMAC || |
| 363 | priv->variant == H6_EMAC) { |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 364 | reg |= SC_RMII_EN | SC_ETCS_EXT_GMII; |
| 365 | break; |
| 366 | } |
| 367 | /* RMII not supported on A83T */ |
| 368 | default: |
| 369 | debug("%s: Invalid PHY interface\n", __func__); |
| 370 | return -EINVAL; |
| 371 | } |
| 372 | |
Icenowy Zheng | 525dc44 | 2018-11-23 00:37:48 +0100 | [diff] [blame] | 373 | if (pdata->tx_delay_ps) |
| 374 | reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET) |
| 375 | & SC_ETXDC_MASK; |
| 376 | |
| 377 | if (pdata->rx_delay_ps) |
| 378 | reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET) |
| 379 | & SC_ERXDC_MASK; |
| 380 | |
Andre Przywara | ba3a96d | 2018-04-04 01:31:16 +0100 | [diff] [blame] | 381 | writel(reg, priv->sysctl_reg + 0x30); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 382 | |
| 383 | return 0; |
| 384 | } |
| 385 | |
| 386 | static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev) |
| 387 | { |
| 388 | struct phy_device *phydev; |
| 389 | |
| 390 | phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); |
| 391 | if (!phydev) |
| 392 | return -ENODEV; |
| 393 | |
| 394 | phy_connect_dev(phydev, dev); |
| 395 | |
| 396 | priv->phydev = phydev; |
| 397 | phy_config(priv->phydev); |
| 398 | |
| 399 | return 0; |
| 400 | } |
| 401 | |
Andre Przywara | 2e7dd26 | 2020-07-06 01:40:40 +0100 | [diff] [blame] | 402 | #define cache_clean_descriptor(desc) \ |
Wolfgang Denk | 62fb2b4 | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 403 | flush_dcache_range((uintptr_t)(desc), \ |
Andre Przywara | 2e7dd26 | 2020-07-06 01:40:40 +0100 | [diff] [blame] | 404 | (uintptr_t)(desc) + sizeof(struct emac_dma_desc)) |
| 405 | |
| 406 | #define cache_inv_descriptor(desc) \ |
| 407 | invalidate_dcache_range((uintptr_t)(desc), \ |
| 408 | (uintptr_t)(desc) + sizeof(struct emac_dma_desc)) |
| 409 | |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 410 | static void rx_descs_init(struct emac_eth_dev *priv) |
| 411 | { |
| 412 | struct emac_dma_desc *desc_table_p = &priv->rx_chain[0]; |
| 413 | char *rxbuffs = &priv->rxbuffer[0]; |
| 414 | struct emac_dma_desc *desc_p; |
Andre Przywara | 4ab675e | 2020-07-06 01:40:41 +0100 | [diff] [blame] | 415 | int i; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 416 | |
Andre Przywara | 7408b09 | 2020-07-06 01:40:37 +0100 | [diff] [blame] | 417 | /* |
| 418 | * Make sure we don't have dirty cache lines around, which could |
| 419 | * be cleaned to DRAM *after* the MAC has already written data to it. |
| 420 | */ |
| 421 | invalidate_dcache_range((uintptr_t)desc_table_p, |
| 422 | (uintptr_t)desc_table_p + sizeof(priv->rx_chain)); |
| 423 | invalidate_dcache_range((uintptr_t)rxbuffs, |
| 424 | (uintptr_t)rxbuffs + sizeof(priv->rxbuffer)); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 425 | |
Andre Przywara | 4ab675e | 2020-07-06 01:40:41 +0100 | [diff] [blame] | 426 | for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) { |
| 427 | desc_p = &desc_table_p[i]; |
| 428 | desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CONFIG_ETH_BUFSIZE]; |
| 429 | desc_p->next = (uintptr_t)&desc_table_p[i + 1]; |
Andre Przywara | 7408b09 | 2020-07-06 01:40:37 +0100 | [diff] [blame] | 430 | desc_p->ctl_size = CONFIG_ETH_RXSIZE; |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 431 | desc_p->status = EMAC_DESC_OWN_DMA; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | /* Correcting the last pointer of the chain */ |
| 435 | desc_p->next = (uintptr_t)&desc_table_p[0]; |
| 436 | |
| 437 | flush_dcache_range((uintptr_t)priv->rx_chain, |
| 438 | (uintptr_t)priv->rx_chain + |
| 439 | sizeof(priv->rx_chain)); |
| 440 | |
| 441 | writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC)); |
| 442 | priv->rx_currdescnum = 0; |
| 443 | } |
| 444 | |
| 445 | static void tx_descs_init(struct emac_eth_dev *priv) |
| 446 | { |
| 447 | struct emac_dma_desc *desc_table_p = &priv->tx_chain[0]; |
| 448 | char *txbuffs = &priv->txbuffer[0]; |
| 449 | struct emac_dma_desc *desc_p; |
Andre Przywara | 4ab675e | 2020-07-06 01:40:41 +0100 | [diff] [blame] | 450 | int i; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 451 | |
Andre Przywara | 4ab675e | 2020-07-06 01:40:41 +0100 | [diff] [blame] | 452 | for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) { |
| 453 | desc_p = &desc_table_p[i]; |
| 454 | desc_p->buf_addr = (uintptr_t)&txbuffs[i * CONFIG_ETH_BUFSIZE]; |
| 455 | desc_p->next = (uintptr_t)&desc_table_p[i + 1]; |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 456 | desc_p->ctl_size = 0; |
Andre Przywara | df6f271 | 2020-07-06 01:40:33 +0100 | [diff] [blame] | 457 | desc_p->status = 0; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 458 | } |
| 459 | |
| 460 | /* Correcting the last pointer of the chain */ |
| 461 | desc_p->next = (uintptr_t)&desc_table_p[0]; |
| 462 | |
Andre Przywara | 8cd8960 | 2020-07-06 01:40:38 +0100 | [diff] [blame] | 463 | /* Flush the first TX buffer descriptor we will tell the MAC about. */ |
Andre Przywara | 2e7dd26 | 2020-07-06 01:40:40 +0100 | [diff] [blame] | 464 | cache_clean_descriptor(desc_table_p); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 465 | |
| 466 | writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC); |
| 467 | priv->tx_currdescnum = 0; |
| 468 | } |
| 469 | |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 470 | static int sun8i_emac_eth_start(struct udevice *dev) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 471 | { |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 472 | struct emac_eth_dev *priv = dev_get_priv(dev); |
Andre Przywara | 874145f | 2020-07-06 01:40:32 +0100 | [diff] [blame] | 473 | int ret; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 474 | |
Andre Przywara | 6bdc70e | 2020-07-06 01:40:42 +0100 | [diff] [blame] | 475 | /* Soft reset MAC */ |
| 476 | writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1); |
| 477 | ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1, |
| 478 | EMAC_CTL1_SOFT_RST, false, 10, true); |
| 479 | if (ret) { |
| 480 | printf("%s: Timeout\n", __func__); |
| 481 | return ret; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 482 | } |
| 483 | |
| 484 | /* Rewrite mac address after reset */ |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 485 | sun8i_eth_write_hwaddr(dev); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 486 | |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 487 | /* transmission starts after the full frame arrived in TX DMA FIFO */ |
| 488 | setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 489 | |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 490 | /* |
| 491 | * RX DMA reads data from RX DMA FIFO to host memory after a |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 492 | * complete frame has been written to RX DMA FIFO |
| 493 | */ |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 494 | setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 495 | |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 496 | /* DMA burst length */ |
| 497 | writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 498 | |
| 499 | /* Initialize rx/tx descriptors */ |
| 500 | rx_descs_init(priv); |
| 501 | tx_descs_init(priv); |
| 502 | |
| 503 | /* PHY Start Up */ |
Andre Przywara | 874145f | 2020-07-06 01:40:32 +0100 | [diff] [blame] | 504 | ret = phy_startup(priv->phydev); |
| 505 | if (ret) |
| 506 | return ret; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 507 | |
| 508 | sun8i_adjust_link(priv, priv->phydev); |
| 509 | |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 510 | /* Start RX/TX DMA */ |
Andre Przywara | 5942282 | 2020-07-06 01:40:43 +0100 | [diff] [blame] | 511 | setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN | |
| 512 | EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM); |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 513 | setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 514 | |
| 515 | /* Enable RX/TX */ |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 516 | setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN); |
| 517 | setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 518 | |
| 519 | return 0; |
| 520 | } |
| 521 | |
| 522 | static int parse_phy_pins(struct udevice *dev) |
| 523 | { |
| 524 | int offset; |
| 525 | const char *pin_name; |
Andre Przywara | 94f3bbd | 2018-04-04 01:31:20 +0100 | [diff] [blame] | 526 | int drive, pull = SUN4I_PINCTRL_NO_PULL, i; |
Andre Przywara | 882a923 | 2021-01-11 21:11:49 +0100 | [diff] [blame] | 527 | u32 iomux; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 528 | |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 529 | offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 530 | "pinctrl-0"); |
| 531 | if (offset < 0) { |
| 532 | printf("WARNING: emac: cannot find pinctrl-0 node\n"); |
| 533 | return offset; |
| 534 | } |
| 535 | |
| 536 | drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, |
Andre Przywara | 26e549b | 2018-04-04 01:31:15 +0100 | [diff] [blame] | 537 | "drive-strength", ~0); |
| 538 | if (drive != ~0) { |
| 539 | if (drive <= 10) |
| 540 | drive = SUN4I_PINCTRL_10_MA; |
| 541 | else if (drive <= 20) |
| 542 | drive = SUN4I_PINCTRL_20_MA; |
| 543 | else if (drive <= 30) |
| 544 | drive = SUN4I_PINCTRL_30_MA; |
| 545 | else |
| 546 | drive = SUN4I_PINCTRL_40_MA; |
Andre Przywara | 26e549b | 2018-04-04 01:31:15 +0100 | [diff] [blame] | 547 | } |
| 548 | |
| 549 | if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL)) |
| 550 | pull = SUN4I_PINCTRL_PULL_UP; |
Andre Przywara | 26e549b | 2018-04-04 01:31:15 +0100 | [diff] [blame] | 551 | else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL)) |
| 552 | pull = SUN4I_PINCTRL_PULL_DOWN; |
Andre Przywara | 94f3bbd | 2018-04-04 01:31:20 +0100 | [diff] [blame] | 553 | |
Andre Przywara | 882a923 | 2021-01-11 21:11:49 +0100 | [diff] [blame] | 554 | /* |
| 555 | * The GPIO pinmux value is an integration choice, so depends on the |
| 556 | * SoC, not the EMAC variant. |
| 557 | */ |
Andre Przywara | 9643c83 | 2021-04-16 00:53:17 +0100 | [diff] [blame] | 558 | if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) |
Andre Przywara | 882a923 | 2021-01-11 21:11:49 +0100 | [diff] [blame] | 559 | iomux = SUN8I_IOMUX_H3; |
| 560 | else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) |
| 561 | iomux = SUN8I_IOMUX_R40; |
| 562 | else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) |
| 563 | iomux = SUN8I_IOMUX_H6; |
| 564 | else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) |
| 565 | iomux = SUN8I_IOMUX_H616; |
Andre Przywara | 9643c83 | 2021-04-16 00:53:17 +0100 | [diff] [blame] | 566 | else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T)) |
Andre Przywara | 882a923 | 2021-01-11 21:11:49 +0100 | [diff] [blame] | 567 | iomux = SUN8I_IOMUX; |
Andre Przywara | 9643c83 | 2021-04-16 00:53:17 +0100 | [diff] [blame] | 568 | else if (IS_ENABLED(CONFIG_MACH_SUN50I)) |
| 569 | iomux = SUN8I_IOMUX; |
| 570 | else |
| 571 | BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins"); |
Andre Przywara | 882a923 | 2021-01-11 21:11:49 +0100 | [diff] [blame] | 572 | |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 573 | for (i = 0; ; i++) { |
| 574 | int pin; |
| 575 | |
Simon Glass | b0ea740 | 2016-10-02 17:59:28 -0600 | [diff] [blame] | 576 | pin_name = fdt_stringlist_get(gd->fdt_blob, offset, |
Andre Przywara | 94f3bbd | 2018-04-04 01:31:20 +0100 | [diff] [blame] | 577 | "pins", i, NULL); |
| 578 | if (!pin_name) |
| 579 | break; |
Andre Przywara | 26e549b | 2018-04-04 01:31:15 +0100 | [diff] [blame] | 580 | |
| 581 | pin = sunxi_name_to_gpio(pin_name); |
| 582 | if (pin < 0) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 583 | continue; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 584 | |
Andre Przywara | 882a923 | 2021-01-11 21:11:49 +0100 | [diff] [blame] | 585 | sunxi_gpio_set_cfgpin(pin, iomux); |
Lothar Felten | acb9a5b | 2018-07-13 10:45:27 +0200 | [diff] [blame] | 586 | |
Andre Przywara | 26e549b | 2018-04-04 01:31:15 +0100 | [diff] [blame] | 587 | if (drive != ~0) |
| 588 | sunxi_gpio_set_drv(pin, drive); |
| 589 | if (pull != ~0) |
| 590 | sunxi_gpio_set_pull(pin, pull); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 591 | } |
| 592 | |
| 593 | if (!i) { |
Andre Przywara | 26e549b | 2018-04-04 01:31:15 +0100 | [diff] [blame] | 594 | printf("WARNING: emac: cannot find pins property\n"); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 595 | return -2; |
| 596 | } |
| 597 | |
| 598 | return 0; |
| 599 | } |
| 600 | |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 601 | static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 602 | { |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 603 | struct emac_eth_dev *priv = dev_get_priv(dev); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 604 | u32 status, desc_num = priv->rx_currdescnum; |
| 605 | struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num]; |
Andre Przywara | 5942282 | 2020-07-06 01:40:43 +0100 | [diff] [blame] | 606 | uintptr_t data_start = (uintptr_t)desc_p->buf_addr; |
| 607 | int length; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 608 | |
| 609 | /* Invalidate entire buffer descriptor */ |
Andre Przywara | 2e7dd26 | 2020-07-06 01:40:40 +0100 | [diff] [blame] | 610 | cache_inv_descriptor(desc_p); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 611 | |
| 612 | status = desc_p->status; |
| 613 | |
| 614 | /* Check for DMA own bit */ |
Andre Przywara | 5942282 | 2020-07-06 01:40:43 +0100 | [diff] [blame] | 615 | if (status & EMAC_DESC_OWN_DMA) |
| 616 | return -EAGAIN; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 617 | |
Andre Przywara | 5942282 | 2020-07-06 01:40:43 +0100 | [diff] [blame] | 618 | length = (status >> 16) & 0x3fff; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 619 | |
Andre Przywara | 5942282 | 2020-07-06 01:40:43 +0100 | [diff] [blame] | 620 | /* make sure we read from DRAM, not our cache */ |
| 621 | invalidate_dcache_range(data_start, |
| 622 | data_start + roundup(length, ARCH_DMA_MINALIGN)); |
| 623 | |
| 624 | if (status & EMAC_DESC_RX_ERROR_MASK) { |
| 625 | debug("RX: packet error: 0x%x\n", |
| 626 | status & EMAC_DESC_RX_ERROR_MASK); |
| 627 | return 0; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 628 | } |
Andre Przywara | 5942282 | 2020-07-06 01:40:43 +0100 | [diff] [blame] | 629 | if (length < 0x40) { |
| 630 | debug("RX: Bad Packet (runt)\n"); |
| 631 | return 0; |
| 632 | } |
| 633 | |
| 634 | if (length > CONFIG_ETH_RXSIZE) { |
| 635 | debug("RX: Too large packet (%d bytes)\n", length); |
| 636 | return 0; |
| 637 | } |
| 638 | |
| 639 | *packetp = (uchar *)(ulong)desc_p->buf_addr; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 640 | |
| 641 | return length; |
| 642 | } |
| 643 | |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 644 | static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 645 | { |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 646 | struct emac_eth_dev *priv = dev_get_priv(dev); |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 647 | u32 desc_num = priv->tx_currdescnum; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 648 | struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num]; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 649 | uintptr_t data_start = (uintptr_t)desc_p->buf_addr; |
| 650 | uintptr_t data_end = data_start + |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 651 | roundup(length, ARCH_DMA_MINALIGN); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 652 | |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 653 | desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 654 | |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 655 | memcpy((void *)data_start, packet, length); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 656 | |
| 657 | /* Flush data to be sent */ |
| 658 | flush_dcache_range(data_start, data_end); |
| 659 | |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 660 | /* frame begin and end */ |
| 661 | desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC; |
| 662 | desc_p->status = EMAC_DESC_OWN_DMA; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 663 | |
Andre Przywara | 2e7dd26 | 2020-07-06 01:40:40 +0100 | [diff] [blame] | 664 | /* make sure the MAC reads the actual data from DRAM */ |
| 665 | cache_clean_descriptor(desc_p); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 666 | |
| 667 | /* Move to next Descriptor and wrap around */ |
| 668 | if (++desc_num >= CONFIG_TX_DESCR_NUM) |
| 669 | desc_num = 0; |
| 670 | priv->tx_currdescnum = desc_num; |
| 671 | |
| 672 | /* Start the DMA */ |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 673 | setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START); |
| 674 | |
| 675 | /* |
| 676 | * Since we copied the data above, we return here without waiting |
| 677 | * for the packet to be actually send out. |
| 678 | */ |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 679 | |
| 680 | return 0; |
| 681 | } |
| 682 | |
Sean Anderson | 4702aa2 | 2020-09-15 10:45:00 -0400 | [diff] [blame] | 683 | static int sun8i_emac_board_setup(struct udevice *dev, |
| 684 | struct emac_eth_dev *priv) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 685 | { |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 686 | int ret; |
| 687 | |
| 688 | ret = clk_enable(&priv->tx_clk); |
| 689 | if (ret) { |
| 690 | dev_err(dev, "failed to enable TX clock\n"); |
| 691 | return ret; |
| 692 | } |
| 693 | |
| 694 | if (reset_valid(&priv->tx_rst)) { |
| 695 | ret = reset_deassert(&priv->tx_rst); |
| 696 | if (ret) { |
| 697 | dev_err(dev, "failed to deassert TX reset\n"); |
| 698 | goto err_tx_clk; |
| 699 | } |
| 700 | } |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 701 | |
Jagan Teki | 727ed79 | 2019-02-28 00:27:00 +0530 | [diff] [blame] | 702 | /* Only H3/H5 have clock controls for internal EPHY */ |
| 703 | if (clk_valid(&priv->ephy_clk)) { |
| 704 | ret = clk_enable(&priv->ephy_clk); |
| 705 | if (ret) { |
| 706 | dev_err(dev, "failed to enable EPHY TX clock\n"); |
| 707 | return ret; |
| 708 | } |
| 709 | } |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 710 | |
Jagan Teki | 727ed79 | 2019-02-28 00:27:00 +0530 | [diff] [blame] | 711 | if (reset_valid(&priv->ephy_rst)) { |
| 712 | ret = reset_deassert(&priv->ephy_rst); |
| 713 | if (ret) { |
| 714 | dev_err(dev, "failed to deassert EPHY TX clock\n"); |
| 715 | return ret; |
Lothar Felten | acb9a5b | 2018-07-13 10:45:27 +0200 | [diff] [blame] | 716 | } |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 717 | } |
| 718 | |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 719 | return 0; |
Lothar Felten | e8cbced | 2018-07-13 10:45:28 +0200 | [diff] [blame] | 720 | |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 721 | err_tx_clk: |
| 722 | clk_disable(&priv->tx_clk); |
| 723 | return ret; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 724 | } |
| 725 | |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 726 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 727 | static int sun8i_mdio_reset(struct mii_dev *bus) |
| 728 | { |
| 729 | struct udevice *dev = bus->priv; |
| 730 | struct emac_eth_dev *priv = dev_get_priv(dev); |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 731 | struct sun8i_eth_pdata *pdata = dev_get_plat(dev); |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 732 | int ret; |
| 733 | |
| 734 | if (!dm_gpio_is_valid(&priv->reset_gpio)) |
| 735 | return 0; |
| 736 | |
| 737 | /* reset the phy */ |
| 738 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); |
| 739 | if (ret) |
| 740 | return ret; |
| 741 | |
| 742 | udelay(pdata->reset_delays[0]); |
| 743 | |
| 744 | ret = dm_gpio_set_value(&priv->reset_gpio, 1); |
| 745 | if (ret) |
| 746 | return ret; |
| 747 | |
| 748 | udelay(pdata->reset_delays[1]); |
| 749 | |
| 750 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); |
| 751 | if (ret) |
| 752 | return ret; |
| 753 | |
| 754 | udelay(pdata->reset_delays[2]); |
| 755 | |
| 756 | return 0; |
| 757 | } |
| 758 | #endif |
| 759 | |
| 760 | static int sun8i_mdio_init(const char *name, struct udevice *priv) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 761 | { |
| 762 | struct mii_dev *bus = mdio_alloc(); |
| 763 | |
| 764 | if (!bus) { |
| 765 | debug("Failed to allocate MDIO bus\n"); |
| 766 | return -ENOMEM; |
| 767 | } |
| 768 | |
| 769 | bus->read = sun8i_mdio_read; |
| 770 | bus->write = sun8i_mdio_write; |
| 771 | snprintf(bus->name, sizeof(bus->name), name); |
| 772 | bus->priv = (void *)priv; |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 773 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 774 | bus->reset = sun8i_mdio_reset; |
| 775 | #endif |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 776 | |
| 777 | return mdio_register(bus); |
| 778 | } |
| 779 | |
Andre Przywara | f58d83c | 2020-10-21 23:21:42 +0530 | [diff] [blame] | 780 | static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet, |
| 781 | int length) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 782 | { |
| 783 | struct emac_eth_dev *priv = dev_get_priv(dev); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 784 | u32 desc_num = priv->rx_currdescnum; |
| 785 | struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num]; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 786 | |
Andre Przywara | 2e7dd26 | 2020-07-06 01:40:40 +0100 | [diff] [blame] | 787 | /* give the current descriptor back to the MAC */ |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 788 | desc_p->status |= EMAC_DESC_OWN_DMA; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 789 | |
| 790 | /* Flush Status field of descriptor */ |
Andre Przywara | 2e7dd26 | 2020-07-06 01:40:40 +0100 | [diff] [blame] | 791 | cache_clean_descriptor(desc_p); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 792 | |
| 793 | /* Move to next desc and wrap-around condition. */ |
| 794 | if (++desc_num >= CONFIG_RX_DESCR_NUM) |
| 795 | desc_num = 0; |
| 796 | priv->rx_currdescnum = desc_num; |
| 797 | |
| 798 | return 0; |
| 799 | } |
| 800 | |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 801 | static void sun8i_emac_eth_stop(struct udevice *dev) |
| 802 | { |
| 803 | struct emac_eth_dev *priv = dev_get_priv(dev); |
| 804 | |
| 805 | /* Stop Rx/Tx transmitter */ |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 806 | clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN); |
| 807 | clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 808 | |
Andre Przywara | e6e29cc | 2020-07-06 01:40:36 +0100 | [diff] [blame] | 809 | /* Stop RX/TX DMA */ |
| 810 | clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN); |
| 811 | clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 812 | |
| 813 | phy_shutdown(priv->phydev); |
| 814 | } |
| 815 | |
| 816 | static int sun8i_emac_eth_probe(struct udevice *dev) |
| 817 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 818 | struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev); |
Icenowy Zheng | 525dc44 | 2018-11-23 00:37:48 +0100 | [diff] [blame] | 819 | struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 820 | struct emac_eth_dev *priv = dev_get_priv(dev); |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 821 | int ret; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 822 | |
| 823 | priv->mac_reg = (void *)pdata->iobase; |
| 824 | |
Sean Anderson | 4702aa2 | 2020-09-15 10:45:00 -0400 | [diff] [blame] | 825 | ret = sun8i_emac_board_setup(dev, priv); |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 826 | if (ret) |
| 827 | return ret; |
| 828 | |
Icenowy Zheng | 525dc44 | 2018-11-23 00:37:48 +0100 | [diff] [blame] | 829 | sun8i_emac_set_syscon(sun8i_pdata, priv); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 830 | |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 831 | sun8i_mdio_init(dev->name, dev); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 832 | priv->bus = miiphy_get_dev_by_name(dev->name); |
| 833 | |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 834 | return sun8i_phy_init(priv, dev); |
| 835 | } |
| 836 | |
| 837 | static const struct eth_ops sun8i_emac_eth_ops = { |
| 838 | .start = sun8i_emac_eth_start, |
| 839 | .write_hwaddr = sun8i_eth_write_hwaddr, |
| 840 | .send = sun8i_emac_eth_send, |
| 841 | .recv = sun8i_emac_eth_recv, |
| 842 | .free_pkt = sun8i_eth_free_pkt, |
| 843 | .stop = sun8i_emac_eth_stop, |
| 844 | }; |
| 845 | |
Andre Przywara | b3ce85c | 2020-10-21 23:27:32 +0530 | [diff] [blame] | 846 | static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv) |
Jagan Teki | 727ed79 | 2019-02-28 00:27:00 +0530 | [diff] [blame] | 847 | { |
Andre Przywara | b3ce85c | 2020-10-21 23:27:32 +0530 | [diff] [blame] | 848 | struct ofnode_phandle_args phandle; |
| 849 | int ret; |
Jagan Teki | 727ed79 | 2019-02-28 00:27:00 +0530 | [diff] [blame] | 850 | |
Andre Przywara | b3ce85c | 2020-10-21 23:27:32 +0530 | [diff] [blame] | 851 | ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle", |
| 852 | NULL, 0, 0, &phandle); |
| 853 | if (ret) |
| 854 | return ret; |
Jagan Teki | 727ed79 | 2019-02-28 00:27:00 +0530 | [diff] [blame] | 855 | |
Andre Przywara | b3ce85c | 2020-10-21 23:27:32 +0530 | [diff] [blame] | 856 | /* If the PHY node is not a child of the internal MDIO bus, we are |
| 857 | * using some external PHY. |
| 858 | */ |
| 859 | if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node), |
| 860 | "allwinner,sun8i-h3-mdio-internal")) |
Emmanuel Vadot | 98be8be | 2019-07-19 22:26:38 +0200 | [diff] [blame] | 861 | return 0; |
| 862 | |
Andre Przywara | b3ce85c | 2020-10-21 23:27:32 +0530 | [diff] [blame] | 863 | ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk); |
Jagan Teki | 727ed79 | 2019-02-28 00:27:00 +0530 | [diff] [blame] | 864 | if (ret) { |
| 865 | dev_err(dev, "failed to get EPHY TX clock\n"); |
| 866 | return ret; |
| 867 | } |
| 868 | |
Andre Przywara | b3ce85c | 2020-10-21 23:27:32 +0530 | [diff] [blame] | 869 | ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst); |
Jagan Teki | 727ed79 | 2019-02-28 00:27:00 +0530 | [diff] [blame] | 870 | if (ret) { |
| 871 | dev_err(dev, "failed to get EPHY TX reset\n"); |
| 872 | return ret; |
| 873 | } |
| 874 | |
| 875 | priv->use_internal_phy = true; |
| 876 | |
| 877 | return 0; |
| 878 | } |
| 879 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 880 | static int sun8i_emac_eth_of_to_plat(struct udevice *dev) |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 881 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 882 | struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev); |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 883 | struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 884 | struct emac_eth_dev *priv = dev_get_priv(dev); |
| 885 | const char *phy_mode; |
Andre Przywara | 94f3bbd | 2018-04-04 01:31:20 +0100 | [diff] [blame] | 886 | const fdt32_t *reg; |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 887 | int node = dev_of_offset(dev); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 888 | int offset = 0; |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 889 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 890 | int reset_flags = GPIOD_IS_OUT; |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 891 | #endif |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 892 | int ret; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 893 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 894 | pdata->iobase = dev_read_addr(dev); |
Andre Przywara | ba3a96d | 2018-04-04 01:31:16 +0100 | [diff] [blame] | 895 | if (pdata->iobase == FDT_ADDR_T_NONE) { |
| 896 | debug("%s: Cannot find MAC base address\n", __func__); |
| 897 | return -EINVAL; |
| 898 | } |
| 899 | |
Lothar Felten | e8cbced | 2018-07-13 10:45:28 +0200 | [diff] [blame] | 900 | priv->variant = dev_get_driver_data(dev); |
| 901 | |
| 902 | if (!priv->variant) { |
| 903 | printf("%s: Missing variant\n", __func__); |
Andre Przywara | 94f3bbd | 2018-04-04 01:31:20 +0100 | [diff] [blame] | 904 | return -EINVAL; |
| 905 | } |
Lothar Felten | e8cbced | 2018-07-13 10:45:28 +0200 | [diff] [blame] | 906 | |
Jagan Teki | cb63d28 | 2019-02-28 00:26:58 +0530 | [diff] [blame] | 907 | ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk); |
| 908 | if (ret) { |
| 909 | dev_err(dev, "failed to get TX clock\n"); |
| 910 | return ret; |
| 911 | } |
| 912 | |
| 913 | ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst); |
| 914 | if (ret && ret != -ENOENT) { |
| 915 | dev_err(dev, "failed to get TX reset\n"); |
| 916 | return ret; |
| 917 | } |
| 918 | |
Jagan Teki | 1cfc64c | 2019-02-28 00:26:51 +0530 | [diff] [blame] | 919 | offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); |
| 920 | if (offset < 0) { |
| 921 | debug("%s: cannot find syscon node\n", __func__); |
| 922 | return -EINVAL; |
| 923 | } |
| 924 | |
| 925 | reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); |
| 926 | if (!reg) { |
| 927 | debug("%s: cannot find reg property in syscon node\n", |
| 928 | __func__); |
| 929 | return -EINVAL; |
| 930 | } |
| 931 | priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, |
| 932 | offset, reg); |
| 933 | if (priv->sysctl_reg == FDT_ADDR_T_NONE) { |
| 934 | debug("%s: Cannot find syscon base address\n", __func__); |
| 935 | return -EINVAL; |
Andre Przywara | ba3a96d | 2018-04-04 01:31:16 +0100 | [diff] [blame] | 936 | } |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 937 | |
| 938 | pdata->phy_interface = -1; |
| 939 | priv->phyaddr = -1; |
| 940 | priv->use_internal_phy = false; |
| 941 | |
Andre Przywara | 94f3bbd | 2018-04-04 01:31:20 +0100 | [diff] [blame] | 942 | offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); |
Andre Przywara | ba3a96d | 2018-04-04 01:31:16 +0100 | [diff] [blame] | 943 | if (offset < 0) { |
| 944 | debug("%s: Cannot find PHY address\n", __func__); |
| 945 | return -EINVAL; |
| 946 | } |
| 947 | priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 948 | |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 949 | phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 950 | |
| 951 | if (phy_mode) |
| 952 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
| 953 | printf("phy interface%d\n", pdata->phy_interface); |
| 954 | |
| 955 | if (pdata->phy_interface == -1) { |
| 956 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); |
| 957 | return -EINVAL; |
| 958 | } |
| 959 | |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 960 | if (priv->variant == H3_EMAC) { |
Andre Przywara | b3ce85c | 2020-10-21 23:27:32 +0530 | [diff] [blame] | 961 | ret = sun8i_handle_internal_phy(dev, priv); |
Jagan Teki | 727ed79 | 2019-02-28 00:27:00 +0530 | [diff] [blame] | 962 | if (ret) |
| 963 | return ret; |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 964 | } |
| 965 | |
| 966 | priv->interface = pdata->phy_interface; |
| 967 | |
| 968 | if (!priv->use_internal_phy) |
| 969 | parse_phy_pins(dev); |
| 970 | |
Icenowy Zheng | 525dc44 | 2018-11-23 00:37:48 +0100 | [diff] [blame] | 971 | sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node, |
| 972 | "allwinner,tx-delay-ps", 0); |
| 973 | if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700) |
| 974 | printf("%s: Invalid TX delay value %d\n", __func__, |
| 975 | sun8i_pdata->tx_delay_ps); |
| 976 | |
| 977 | sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node, |
| 978 | "allwinner,rx-delay-ps", 0); |
| 979 | if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100) |
| 980 | printf("%s: Invalid RX delay value %d\n", __func__, |
| 981 | sun8i_pdata->rx_delay_ps); |
| 982 | |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 983 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Simon Glass | 7a49443 | 2017-05-17 17:18:09 -0600 | [diff] [blame] | 984 | if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 985 | "snps,reset-active-low")) |
| 986 | reset_flags |= GPIOD_ACTIVE_LOW; |
| 987 | |
| 988 | ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, |
| 989 | &priv->reset_gpio, reset_flags); |
| 990 | |
| 991 | if (ret == 0) { |
Simon Glass | 7a49443 | 2017-05-17 17:18:09 -0600 | [diff] [blame] | 992 | ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), |
Philipp Tomsich | 3297b55 | 2017-02-22 19:46:41 +0100 | [diff] [blame] | 993 | "snps,reset-delays-us", |
| 994 | sun8i_pdata->reset_delays, 3); |
| 995 | } else if (ret == -ENOENT) { |
| 996 | ret = 0; |
| 997 | } |
| 998 | #endif |
| 999 | |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 1000 | return 0; |
| 1001 | } |
| 1002 | |
| 1003 | static const struct udevice_id sun8i_emac_eth_ids[] = { |
| 1004 | {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC }, |
| 1005 | {.compatible = "allwinner,sun50i-a64-emac", |
| 1006 | .data = (uintptr_t)A64_EMAC }, |
| 1007 | {.compatible = "allwinner,sun8i-a83t-emac", |
| 1008 | .data = (uintptr_t)A83T_EMAC }, |
Lothar Felten | e8cbced | 2018-07-13 10:45:28 +0200 | [diff] [blame] | 1009 | {.compatible = "allwinner,sun8i-r40-gmac", |
| 1010 | .data = (uintptr_t)R40_GMAC }, |
Samuel Holland | 3386e9a | 2020-05-07 18:10:51 -0500 | [diff] [blame] | 1011 | {.compatible = "allwinner,sun50i-h6-emac", |
| 1012 | .data = (uintptr_t)H6_EMAC }, |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 1013 | { } |
| 1014 | }; |
| 1015 | |
| 1016 | U_BOOT_DRIVER(eth_sun8i_emac) = { |
| 1017 | .name = "eth_sun8i_emac", |
| 1018 | .id = UCLASS_ETH, |
| 1019 | .of_match = sun8i_emac_eth_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 1020 | .of_to_plat = sun8i_emac_eth_of_to_plat, |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 1021 | .probe = sun8i_emac_eth_probe, |
| 1022 | .ops = &sun8i_emac_eth_ops, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 1023 | .priv_auto = sizeof(struct emac_eth_dev), |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 1024 | .plat_auto = sizeof(struct sun8i_eth_pdata), |
Amit Singh Tomar | d194c0e | 2016-07-06 17:59:44 +0530 | [diff] [blame] | 1025 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
| 1026 | }; |