blob: 711ae5bc29d9256fcf1dd3b796fadf9fbcd70380 [file] [log] [blame]
Patrick Delaunayd6e53c72018-10-26 09:02:52 +02001# SPDX-License-Identifier: GPL-2.0+
Simon Glass36ad2342015-06-23 15:39:15 -06002#
3# Copyright (c) 2015 Google, Inc
4# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5#
Simon Glass36ad2342015-06-23 15:39:15 -06006
Anup Patel8d28c3c2019-02-25 08:14:55 +00007obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
8obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
9obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
Peng Fan0f085152019-07-31 07:01:34 +000010obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020011obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
Peng Fan2d9bd932019-07-31 07:01:54 +000012obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
Stephen Warrene8e3f202016-08-08 11:28:24 -060013
Anup Patel00a156d2019-06-25 06:31:02 +000014obj-y += analogbits/
Peng Fan5e80d5a2018-10-18 14:28:30 +020015obj-y += imx/
Stephen Warrene8e3f202016-08-08 11:28:24 -060016obj-y += tegra/
Dario Binacchida3b0202020-12-30 00:06:32 +010017obj-y += ti/
Mario Sixd290e272018-01-15 11:06:54 +010018obj-$(CONFIG_ARCH_ASPEED) += aspeed/
developer2186c982018-11-15 10:07:54 +080019obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
developer2bef3c52019-09-25 17:45:21 +080020obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
Jerome Brunet3da39a82019-02-10 14:54:30 +010021obj-$(CONFIG_ARCH_MESON) += meson/
Mario Sixd290e272018-01-15 11:06:54 +010022obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
Marek Vasut3f9d7352018-07-31 17:58:07 +020023obj-$(CONFIG_ARCH_SOCFPGA) += altera/
Wenyou Yang8c772bd2016-07-20 17:55:12 +080024obj-$(CONFIG_CLK_AT91) += at91/
Marek Behún61d74e82018-04-24 17:21:25 +020025obj-$(CONFIG_CLK_MVEBU) += mvebu/
Álvaro Fernández Rojasc35611c2017-05-07 20:13:01 +020026obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
Paul Burton0399f442016-09-08 07:47:38 +010027obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
Mario Sixd290e272018-01-15 11:06:54 +010028obj-$(CONFIG_CLK_EXYNOS) += exynos/
Simon Glass6eb4e3c2020-02-06 09:54:53 -070029obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +030030obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
Sean Anderson152919d2021-06-11 00:16:14 -040031obj-$(CONFIG_CLK_K210) += clk_kendryte.o
Mario Six7cab1472018-08-06 10:23:36 +020032obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
Padmarao Begari0c4ae802021-01-15 08:20:38 +053033obj-$(CONFIG_CLK_MPFS) += microchip/
Stefan Roese560b07f2020-07-30 13:56:16 +020034obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
Manivannan Sadhasivam91a85132018-06-14 23:38:35 +053035obj-$(CONFIG_CLK_OWL) += owl/
Mario Sixd290e272018-01-15 11:06:54 +010036obj-$(CONFIG_CLK_RENESAS) += renesas/
Etienne Carriere78928e12020-09-09 18:44:04 +020037obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
Anup Patel42fdf082019-02-25 08:14:49 +000038obj-$(CONFIG_CLK_SIFIVE) += sifive/
Jagan Teki1d150b42018-12-22 21:32:49 +053039obj-$(CONFIG_ARCH_SUNXI) += sunxi/
Patrice Chotardd4f2d202017-11-15 13:14:48 +010040obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
Patrick Delaunaye6ab6272018-03-12 10:46:15 +010041obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
Mario Sixd290e272018-01-15 11:06:54 +010042obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
Liviu Dudauba024e62018-09-17 17:50:00 +010043obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
Mario Sixd290e272018-01-15 11:06:54 +010044obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
45obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
Zhengxun39df0532021-06-11 15:10:48 +000046obj-$(CONFIG_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
Mario Sixa3c07062018-04-27 14:53:15 +020047obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
Mario Sixd290e272018-01-15 11:06:54 +010048obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
49obj-$(CONFIG_SANDBOX) += clk_sandbox.o
50obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
Lukasz Majewski8c0709b2019-06-24 15:50:50 +020051obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
Patrice Chotard5fffeab2017-09-13 18:00:06 +020052obj-$(CONFIG_STM32H7) += clk_stm32h7.o
Siva Durga Prasad Paladuguf7a71202019-06-23 12:24:57 +053053obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
Tero Kristo814c6112019-09-27 19:14:26 +030054obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
Adam Forddb7b2f42021-06-04 12:26:06 -050055obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o