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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Christian Gmeiner5ad7c162014-10-02 13:33:46 +02002/*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014 Bachmann electronic GmbH
Christian Gmeiner5ad7c162014-10-02 13:33:46 +02005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10#include "mx6_common.h"
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020011
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020012/* Size of malloc() pool */
13#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
14
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020015/* UART Configs */
16#define CONFIG_MXC_UART
17#define CONFIG_MXC_UART_BASE UART1_BASE
18
19/* SF Configs */
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020020#define CONFIG_SF_DEFAULT_BUS 2
Christian Gmeiner477b5322014-10-22 11:29:51 +020021#define CONFIG_SF_DEFAULT_CS 0
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020022#define CONFIG_SF_DEFAULT_SPEED 25000000
23#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
24
25/* IO expander */
26#define CONFIG_PCA953X
27#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
28#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020029
30/* I2C Configs */
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020031#define CONFIG_SYS_I2C
32#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +020033#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
34#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf1a52162015-03-20 10:20:40 -070035#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020036#define CONFIG_SYS_I2C_SPEED 100000
37
38/* OCOTP Configs */
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020039#define CONFIG_IMX_OTP
40#define IMX_OTP_BASE OCOTP_BASE_ADDR
41#define IMX_OTP_ADDR_MAX 0x7F
42#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
43#define IMX_OTPWRITE_ENABLED
44
45/* MMC Configs */
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020046#define CONFIG_SYS_FSL_ESDHC_ADDR 0
47#define CONFIG_SYS_FSL_USDHC_NUM 2
48
Christian Gmeinerb2a03fd2014-11-10 14:35:48 +010049/* USB Configs */
Christian Gmeinerb2a03fd2014-11-10 14:35:48 +010050#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
51#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
52
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020053/*
54 * SATA Configs
55 */
56#ifdef CONFIG_CMD_SATA
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020057#define CONFIG_SYS_SATA_MAX_DEVICE 1
58#define CONFIG_DWC_AHSATA_PORT_ID 0
59#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
60#define CONFIG_LBA48
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020061#endif
62
Christian Gmeinerd8e33c42015-01-19 17:26:48 +010063/* SPL */
64#ifdef CONFIG_SPL
65#include "imx6_spl.h"
Christian Gmeinerd8e33c42015-01-19 17:26:48 +010066#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
Christian Gmeinerd8e33c42015-01-19 17:26:48 +010067#endif
68
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020069#define CONFIG_FEC_MXC
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020070#define IMX_FEC_BASE ENET_BASE_ADDR
71#define CONFIG_FEC_XCV_TYPE MII100
72#define CONFIG_ETHPRIME "FEC"
73#define CONFIG_FEC_MXC_PHYADDR 0x5
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020074#define CONFIG_PHY_SMSC
75
Christian Gmeinerf2a73992015-02-11 15:20:25 +010076#ifndef CONFIG_SPL
Christian Gmeinerf2a73992015-02-11 15:20:25 +010077#define CONFIG_ENV_EEPROM_IS_ON_I2C
78#define CONFIG_SYS_I2C_EEPROM_BUS 1
79#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
80#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
81#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
Christian Gmeinerf2a73992015-02-11 15:20:25 +010082#endif
83
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020084#define CONFIG_PREBOOT ""
85
Christian Gmeiner2f1d2412017-06-08 09:37:26 +020086/* Thermal support */
87#define CONFIG_IMX_THERMAL
88
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020089/* Physical Memory Map */
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020090#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
Christian Gmeiner5ad7c162014-10-02 13:33:46 +020091
92#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
93#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
94#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
95
96#define CONFIG_SYS_INIT_SP_OFFSET \
97 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
98#define CONFIG_SYS_INIT_SP_ADDR \
99 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
100
Peter Robinson4b671502015-05-22 17:30:45 +0100101/* Environment organization */
Christian Gmeiner5ad7c162014-10-02 13:33:46 +0200102#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
103#define CONFIG_ENV_OFFSET (1024 * 1024)
104/* M25P16 has an erase size of 64 KiB */
105#define CONFIG_ENV_SECT_SIZE (64 * 1024)
106#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
107#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
108#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
109#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
110
Christian Gmeiner5ad7c162014-10-02 13:33:46 +0200111#define CONFIG_BOOTP_SERVERIP
112#define CONFIG_BOOTP_BOOTFILE
113
114#endif /* __CONFIG_H */