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wdenk3d818262002-09-22 23:07:35 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28/*
29 * CPU specific code
30 */
31
32#include <common.h>
33#include <command.h>
34#include <arm920t.h>
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020035#include <asm/system.h>
wdenk3d818262002-09-22 23:07:35 +000036
Wolfgang Denk6405a152006-03-31 18:32:53 +020037#ifdef CONFIG_USE_IRQ
38DECLARE_GLOBAL_DATA_PTR;
39#endif
40
wdenk3d818262002-09-22 23:07:35 +000041static void cp_delay (void)
42{
43 volatile int i;
44
45 /* copro seems to need some delay between reading and writing */
46 for (i = 0; i < 100; i++);
47}
48
wdenk3d818262002-09-22 23:07:35 +000049int cpu_init (void)
50{
51 /*
wdenkc0aa5c52003-12-06 19:49:23 +000052 * setup up stacks if necessary
wdenk3d818262002-09-22 23:07:35 +000053 */
54#ifdef CONFIG_USE_IRQ
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020055 IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
wdenkc0aa5c52003-12-06 19:49:23 +000056 FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
57#endif
58 return 0;
wdenk3d818262002-09-22 23:07:35 +000059}
60
61int cleanup_before_linux (void)
62{
63 /*
64 * this function is called just before we call linux
65 * it prepares the processor for linux
66 *
67 * we turn off caches etc ...
68 */
69
70 unsigned long i;
71
72 disable_interrupts ();
73
74 /* turn off I/D-cache */
75 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020076 i &= ~(CR_C | CR_I);
wdenk3d818262002-09-22 23:07:35 +000077 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
78
79 /* flush I/D-cache */
80 i = 0;
81 asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
Wolfgang Denkadf20a12005-09-25 01:48:28 +020082
wdenk3d818262002-09-22 23:07:35 +000083 return (0);
84}
85
86int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
87{
wdenk3d818262002-09-22 23:07:35 +000088 disable_interrupts ();
89 reset_cpu (0);
90 /*NOTREACHED*/
91 return (0);
92}
93
94void icache_enable (void)
95{
96 ulong reg;
97
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020098 reg = get_cr (); /* get control reg. */
wdenk3d818262002-09-22 23:07:35 +000099 cp_delay ();
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200100 set_cr (reg | CR_I);
wdenk3d818262002-09-22 23:07:35 +0000101}
102
103void icache_disable (void)
104{
105 ulong reg;
106
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200107 reg = get_cr ();
wdenk3d818262002-09-22 23:07:35 +0000108 cp_delay ();
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200109 set_cr (reg & ~CR_I);
wdenk3d818262002-09-22 23:07:35 +0000110}
111
112int icache_status (void)
113{
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200114 return (get_cr () & CR_I) != 0;
wdenk3d818262002-09-22 23:07:35 +0000115}
116
117#ifdef USE_920T_MMU
118/* It makes no sense to use the dcache if the MMU is not enabled */
119void dcache_enable (void)
120{
121 ulong reg;
122
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200123 reg = get_cr ();
wdenk3d818262002-09-22 23:07:35 +0000124 cp_delay ();
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200125 set_cr (reg | CR_C);
wdenk3d818262002-09-22 23:07:35 +0000126}
127
128void dcache_disable (void)
129{
130 ulong reg;
131
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200132 reg = get_cr ();
wdenk3d818262002-09-22 23:07:35 +0000133 cp_delay ();
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200134 reg &= ~CR_C;
135 set_cr (reg);
wdenk3d818262002-09-22 23:07:35 +0000136}
137
138int dcache_status (void)
139{
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200140 return (get_cr () & CR_C) != 0;
wdenk3d818262002-09-22 23:07:35 +0000141}
142#endif