masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 1 | /* |
| 2 | * include/configs/blanche.h |
| 3 | * This file is blanche board configuration. |
| 4 | * |
| 5 | * Copyright (C) 2016 Renesas Electronics Corporation |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0 |
| 8 | */ |
| 9 | |
| 10 | #ifndef __BLANCHE_H |
| 11 | #define __BLANCHE_H |
| 12 | |
| 13 | #undef DEBUG |
| 14 | #define CONFIG_R8A7792 |
| 15 | #define CONFIG_RMOBILE_BOARD_STRING "Blanche" |
| 16 | |
| 17 | #include "rcar-gen2-common.h" |
| 18 | |
masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 19 | /* STACK */ |
| 20 | #define CONFIG_SYS_INIT_SP_ADDR 0xE817FFFC |
| 21 | #define STACK_AREA_SIZE 0xC000 |
| 22 | #define LOW_LEVEL_MERAM_STACK \ |
| 23 | (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) |
| 24 | |
| 25 | /* MEMORY */ |
| 26 | #define RCAR_GEN2_SDRAM_BASE 0x40000000 |
| 27 | #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) |
| 28 | #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) |
| 29 | |
| 30 | /* SCIF */ |
masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 31 | #define CONFIG_CONS_SCIF0 |
| 32 | |
| 33 | #define CONFIG_SYS_MEMTEST_START (RCAR_GEN2_SDRAM_BASE) |
| 34 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 504 * 1024 * 1024) |
| 35 | |
| 36 | #undef CONFIG_SYS_ALT_MEMTEST |
| 37 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
| 38 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
| 39 | |
| 40 | /* FLASH */ |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 41 | #if !defined(CONFIG_MTD_NOR_FLASH) |
masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 42 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
| 43 | #define CONFIG_SPI |
| 44 | #define CONFIG_SH_QSPI |
| 45 | #define CONFIG_SH_QSPI_BASE 0xE6B10000 |
| 46 | #else |
| 47 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
| 48 | #define CONFIG_SYS_FLASH_CFI |
| 49 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| 50 | #define CONFIG_FLASH_CFI_DRIVER |
| 51 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
| 52 | #define CONFIG_FLASH_SHOW_PROGRESS 45 |
| 53 | #define CONFIG_SYS_FLASH_BASE 0x00000000 |
| 54 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ |
| 55 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 |
| 56 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 57 | #define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } |
| 58 | #define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } |
| 59 | |
| 60 | #define CONFIG_SYS_FLASH_ERASE_TOUT 3000 |
| 61 | #define CONFIG_SYS_FLASH_WRITE_TOUT 3000 |
| 62 | #define CONFIG_SYS_FLASH_LOCK_TOUT 3000 |
| 63 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 |
masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 64 | #undef CONFIG_CMD_SF |
| 65 | #undef CONFIG_CMD_SPI |
| 66 | #endif |
| 67 | |
masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 68 | |
| 69 | /* Board Clock */ |
| 70 | #define RMOBILE_XTAL_CLK 20000000u |
| 71 | #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK |
| 72 | #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ |
| 73 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
| 74 | |
| 75 | /* ENV setting */ |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 76 | #if !defined(CONFIG_MTD_NOR_FLASH) |
masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 77 | #else |
masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 78 | #undef CONFIG_ENV_ADDR |
masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 79 | #define CONFIG_ENV_SECT_SIZE (256 * 1024) |
| 80 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
| 81 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) |
| 82 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) |
| 83 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) |
| 84 | #endif |
| 85 | |
masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 86 | /* Module stop status bits */ |
| 87 | /* INTC-RT */ |
| 88 | #define CONFIG_SMSTP0_ENA 0x00400000 |
| 89 | /* SDHI0 */ |
| 90 | #define CONFIG_SMSTP3_ENA 0x00004000 |
| 91 | /* INTC-SYS, IRQC */ |
| 92 | #define CONFIG_SMSTP4_ENA 0x00000180 |
| 93 | /* SCIF0 */ |
| 94 | #define CONFIG_SMSTP7_ENA 0x00200000 |
| 95 | /* QSPI */ |
| 96 | #define CONFIG_SMSTP9_ENA 0x00020000 |
| 97 | /* SYS-DMAC0 */ |
| 98 | #define CONFIG_RMSTP2_ENA 0x00080000 |
| 99 | |
| 100 | /* SDHI */ |
| 101 | #define CONFIG_SH_SDHI_FREQ 97500000 |
Nobuhiro Iwamatsu | 5a9900f | 2016-05-31 04:28:11 +0900 | [diff] [blame] | 102 | #define HAVE_BLOCK_DEVICE |
masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 103 | |
| 104 | #endif /* __BLANCHE_H */ |