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git01.mediatek.com / filogic / uboot / 9004ee03691618245d529fe409a96cc58b8eaaeb / . / include / configs / socfpga_arria5_socdk.h
blob: 8d62d1307e571b780bd5c38e016bf4362e489422 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Marek Vasut69295472014-12-30 18:16:08 +0100[diff] [blame]2/*
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
Marek Vasut69295472014-12-30 18:16:08 +0100[diff] [blame]4 */
5#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
6#define __CONFIG_SOCFPGA_ARRIA5_H__
7
Dinh Nguyeneca8b5c2015-11-23 17:27:17 -0600[diff] [blame]8#include <asm/arch/base_addr_ac5.h>
Marek Vasut69295472014-12-30 18:16:08 +0100[diff] [blame]9
Marek Vasut69295472014-12-30 18:16:08 +0100[diff] [blame]10/* Memory configurations */
11#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
12
13/* Booting Linux */
Tom Rini9004ee02021-08-23 10:25:30 -0400[diff] [blame^]14#define CONFIG_SYS_LOAD_ADDR 0x01000000
Marek Vasut69295472014-12-30 18:16:08 +0100[diff] [blame]15
Marek Vasut69295472014-12-30 18:16:08 +0100[diff] [blame]16/* The rest of the configuration is shared */
17#include <configs/socfpga_common.h>
18
19#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */