blob: 3b25c5b7a75d735dfc7caa43017c996f0634dc48 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Rick Chen6eedd922017-12-26 13:55:49 +08002/*
3 * Copyright (c) 2016-17 Microsemi Corporation.
4 * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
5 *
6 * Copyright (C) 2017 Andes Technology Corporation
7 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
Rick Chen6eedd922017-12-26 13:55:49 +08008 */
9
10#include <common.h>
Simon Glass9b61c7c2019-11-14 12:57:41 -070011#include <irq_func.h>
Rick Chen6eedd922017-12-26 13:55:49 +080012#include <asm/ptrace.h>
13#include <asm/system.h>
14#include <asm/encoding.h>
15
Bin Mengbcc6c742018-12-12 06:12:44 -080016static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
17{
18 static const char * const exception_code[] = {
19 "Instruction address misaligned",
20 "Instruction access fault",
21 "Illegal instruction",
22 "Breakpoint",
23 "Load address misaligned",
24 "Load access fault",
25 "Store/AMO address misaligned",
26 "Store/AMO access fault",
27 "Environment call from U-mode",
28 "Environment call from S-mode",
29 "Reserved",
30 "Environment call from M-mode",
31 "Instruction page fault",
32 "Load page fault",
33 "Reserved",
34 "Store/AMO page fault",
35 };
36
37 if (code < ARRAY_SIZE(exception_code)) {
38 printf("exception code: %ld , %s , epc %lx , ra %lx\n",
39 code, exception_code[code], epc, regs->ra);
40 } else {
Lukas Auer8318e892019-01-04 01:37:28 +010041 printf("reserved exception code: %ld , epc %lx , ra %lx\n",
42 code, epc, regs->ra);
Bin Mengbcc6c742018-12-12 06:12:44 -080043 }
44
45 hang();
46}
Rick Chen6eedd922017-12-26 13:55:49 +080047
48int interrupt_init(void)
49{
50 return 0;
51}
52
53/*
54 * enable interrupts
55 */
56void enable_interrupts(void)
57{
58}
59
60/*
61 * disable interrupts
62 */
63int disable_interrupts(void)
64{
65 return 0;
66}
67
Anup Patel89b39342018-12-03 10:57:40 +053068ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs)
Rick Chen6eedd922017-12-26 13:55:49 +080069{
Anup Patel89b39342018-12-03 10:57:40 +053070 ulong is_irq, irq;
71
72 is_irq = (cause & MCAUSE_INT);
73 irq = (cause & ~MCAUSE_INT);
Rick Chen6eedd922017-12-26 13:55:49 +080074
Anup Patel89b39342018-12-03 10:57:40 +053075 if (is_irq) {
76 switch (irq) {
77 case IRQ_M_EXT:
78 case IRQ_S_EXT:
79 external_interrupt(0); /* handle external interrupt */
80 break;
81 case IRQ_M_TIMER:
82 case IRQ_S_TIMER:
83 timer_interrupt(0); /* handle timer interrupt */
84 break;
85 default:
86 _exit_trap(cause, epc, regs);
87 break;
88 };
89 } else {
90 _exit_trap(cause, epc, regs);
91 }
Rick Chen6eedd922017-12-26 13:55:49 +080092
93 return epc;
94}
95
96/*
97 *Entry Point for PLIC Interrupt Handler
98 */
99__attribute__((weak)) void external_interrupt(struct pt_regs *regs)
100{
101}
102
103__attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
104{
105}