Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016 Atmel Corporation |
| 4 | * Wenyou.Yang <wenyou.yang@atmel.com> |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <clk-uclass.h> |
Simon Glass | 11c89f3 | 2017-05-17 17:18:03 -0600 | [diff] [blame] | 9 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 10 | #include <log.h> |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 11 | #include <dm/lists.h> |
Heiko Stübner | 9a2cdca | 2017-02-18 19:46:21 +0100 | [diff] [blame] | 12 | #include <dm/util.h> |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 13 | #include "pmc.h" |
| 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 17 | static const struct udevice_id at91_pmc_match[] = { |
Wenyou Yang | 217c968 | 2017-04-14 14:53:24 +0800 | [diff] [blame] | 18 | { .compatible = "atmel,at91rm9200-pmc" }, |
| 19 | { .compatible = "atmel,at91sam9260-pmc" }, |
| 20 | { .compatible = "atmel,at91sam9g45-pmc" }, |
| 21 | { .compatible = "atmel,at91sam9n12-pmc" }, |
| 22 | { .compatible = "atmel,at91sam9x5-pmc" }, |
| 23 | { .compatible = "atmel,sama5d3-pmc" }, |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 24 | { .compatible = "atmel,sama5d2-pmc" }, |
| 25 | {} |
| 26 | }; |
| 27 | |
Walter Lozano | 2901ac6 | 2020-06-25 01:10:04 -0300 | [diff] [blame] | 28 | U_BOOT_DRIVER(atmel_at91rm9200_pmc) = { |
| 29 | .name = "atmel_at91rm9200_pmc", |
Wenyou Yang | e400930 | 2016-09-13 10:25:55 +0800 | [diff] [blame] | 30 | .id = UCLASS_SIMPLE_BUS, |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 31 | .of_match = at91_pmc_match, |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 32 | }; |
| 33 | |
Walter Lozano | 48e5b04 | 2020-06-25 01:10:06 -0300 | [diff] [blame] | 34 | U_BOOT_DRIVER_ALIAS(atmel_at91rm9200_pmc, atmel_at91sam9260_pmc) |
| 35 | |
Wenyou Yang | 9a71d39 | 2016-09-27 11:00:29 +0800 | [diff] [blame] | 36 | /*---------------------------------------------------------*/ |
| 37 | |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 38 | int at91_pmc_core_probe(struct udevice *dev) |
| 39 | { |
| 40 | struct pmc_platdata *plat = dev_get_platdata(dev); |
| 41 | |
| 42 | dev = dev_get_parent(dev); |
| 43 | |
Masahiro Yamada | 32822d0 | 2020-08-04 14:14:43 +0900 | [diff] [blame] | 44 | plat->reg_base = dev_read_addr_ptr(dev); |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 45 | |
| 46 | return 0; |
| 47 | } |
| 48 | |
Wenyou Yang | 9a71d39 | 2016-09-27 11:00:29 +0800 | [diff] [blame] | 49 | /** |
| 50 | * at91_clk_sub_device_bind() - for the at91 clock driver |
| 51 | * Recursively bind its children as clk devices. |
| 52 | * |
| 53 | * @return: 0 on success, or negative error code on failure |
| 54 | */ |
| 55 | int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name) |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 56 | { |
| 57 | const void *fdt = gd->fdt_blob; |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 58 | int offset = dev_of_offset(dev); |
Wenyou Yang | 9a71d39 | 2016-09-27 11:00:29 +0800 | [diff] [blame] | 59 | bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC); |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 60 | const char *name; |
| 61 | int ret; |
| 62 | |
| 63 | for (offset = fdt_first_subnode(fdt, offset); |
| 64 | offset > 0; |
| 65 | offset = fdt_next_subnode(fdt, offset)) { |
Wenyou Yang | 9a71d39 | 2016-09-27 11:00:29 +0800 | [diff] [blame] | 66 | if (pre_reloc_only && |
Patrick Delaunay | 9d0731d | 2020-04-03 11:39:18 +0200 | [diff] [blame] | 67 | !ofnode_pre_reloc(offset_to_ofnode(offset))) |
Wenyou Yang | 9a71d39 | 2016-09-27 11:00:29 +0800 | [diff] [blame] | 68 | continue; |
| 69 | /* |
| 70 | * If this node has "compatible" property, this is not |
| 71 | * a clock sub-node, but a normal device. skip. |
| 72 | */ |
| 73 | fdt_get_property(fdt, offset, "compatible", &ret); |
| 74 | if (ret >= 0) |
| 75 | continue; |
| 76 | |
| 77 | if (ret != -FDT_ERR_NOTFOUND) |
| 78 | return ret; |
| 79 | |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 80 | name = fdt_get_name(fdt, offset, NULL); |
| 81 | if (!name) |
| 82 | return -EINVAL; |
Wenyou Yang | 9a71d39 | 2016-09-27 11:00:29 +0800 | [diff] [blame] | 83 | ret = device_bind_driver_to_node(dev, drv_name, name, |
Simon Glass | e6dd8da | 2017-05-18 20:09:07 -0600 | [diff] [blame] | 84 | offset_to_ofnode(offset), NULL); |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 85 | if (ret) |
| 86 | return ret; |
| 87 | } |
| 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
Simon Glass | b7ae277 | 2017-05-18 20:09:40 -0600 | [diff] [blame] | 92 | int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) |
Wenyou Yang | 9a71d39 | 2016-09-27 11:00:29 +0800 | [diff] [blame] | 93 | { |
| 94 | int periph; |
| 95 | |
| 96 | if (args->args_count) { |
| 97 | debug("Invalid args_count: %d\n", args->args_count); |
| 98 | return -EINVAL; |
| 99 | } |
| 100 | |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 101 | periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg", |
| 102 | -1); |
Wenyou Yang | 9a71d39 | 2016-09-27 11:00:29 +0800 | [diff] [blame] | 103 | if (periph < 0) |
| 104 | return -EINVAL; |
| 105 | |
| 106 | clk->id = periph; |
| 107 | |
| 108 | return 0; |
| 109 | } |
| 110 | |
| 111 | int at91_clk_probe(struct udevice *dev) |
| 112 | { |
| 113 | struct udevice *dev_periph_container, *dev_pmc; |
| 114 | struct pmc_platdata *plat = dev_get_platdata(dev); |
| 115 | |
| 116 | dev_periph_container = dev_get_parent(dev); |
| 117 | dev_pmc = dev_get_parent(dev_periph_container); |
| 118 | |
Masahiro Yamada | 32822d0 | 2020-08-04 14:14:43 +0900 | [diff] [blame] | 119 | plat->reg_base = dev_read_addr_ptr(dev_pmc); |
Wenyou Yang | 9a71d39 | 2016-09-27 11:00:29 +0800 | [diff] [blame] | 120 | |
| 121 | return 0; |
| 122 | } |
Claudiu Beznea | 8fdb425 | 2020-09-07 17:46:38 +0300 | [diff] [blame^] | 123 | |
| 124 | /** |
| 125 | * pmc_read() - read content at address base + off into val |
| 126 | * |
| 127 | * @base: base address |
| 128 | * @off: offset to read from |
| 129 | * @val: where the content of base + off is stored |
| 130 | * |
| 131 | * @return: void |
| 132 | */ |
| 133 | void pmc_read(void __iomem *base, unsigned int off, unsigned int *val) |
| 134 | { |
| 135 | *val = readl(base + off); |
| 136 | } |
| 137 | |
| 138 | /** |
| 139 | * pmc_write() - write content of val at address base + off |
| 140 | * |
| 141 | * @base: base address |
| 142 | * @off: offset to write to |
| 143 | * @val: content to be written at base + off |
| 144 | * |
| 145 | * @return: void |
| 146 | */ |
| 147 | void pmc_write(void __iomem *base, unsigned int off, unsigned int val) |
| 148 | { |
| 149 | writel(val, base + off); |
| 150 | } |
| 151 | |
| 152 | /** |
| 153 | * pmc_update_bits() - update a set of bits at address base + off |
| 154 | * |
| 155 | * @base: base address |
| 156 | * @off: offset to be updated |
| 157 | * @mask: mask of bits to be updated |
| 158 | * @bits: the new value to be updated |
| 159 | * |
| 160 | * @return: void |
| 161 | */ |
| 162 | void pmc_update_bits(void __iomem *base, unsigned int off, |
| 163 | unsigned int mask, unsigned int bits) |
| 164 | { |
| 165 | unsigned int tmp; |
| 166 | |
| 167 | tmp = readl(base + off); |
| 168 | tmp &= ~mask; |
| 169 | writel(tmp | (bits & mask), base + off); |
| 170 | } |
| 171 | |
| 172 | /** |
| 173 | * at91_clk_mux_val_to_index() - get parent index in mux table |
| 174 | * |
| 175 | * @table: clock mux table |
| 176 | * @num_parents: clock number of parents |
| 177 | * @val: clock id who's mux index should be retrieved |
| 178 | * |
| 179 | * @return: clock index in mux table or a negative error number in case of |
| 180 | * failure |
| 181 | */ |
| 182 | int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val) |
| 183 | { |
| 184 | int i; |
| 185 | |
| 186 | if (!table || !num_parents) |
| 187 | return -EINVAL; |
| 188 | |
| 189 | for (i = 0; i < num_parents; i++) { |
| 190 | if (table[i] == val) |
| 191 | return i; |
| 192 | } |
| 193 | |
| 194 | return -EINVAL; |
| 195 | } |
| 196 | |
| 197 | /** |
| 198 | * at91_clk_mux_index_to_val() - get parent ID corresponding to an entry in |
| 199 | * clock's mux table |
| 200 | * |
| 201 | * @table: clock's mux table |
| 202 | * @num_parents: clock's number of parents |
| 203 | * @index: index in mux table which clock's ID should be retrieved |
| 204 | * |
| 205 | * @return: clock ID or a negative error number in case of failure |
| 206 | */ |
| 207 | int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index) |
| 208 | { |
| 209 | if (!table || !num_parents || index < 0 || index > num_parents) |
| 210 | return -EINVAL; |
| 211 | |
| 212 | return table[index]; |
| 213 | } |