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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wenyou Yang8c772bd2016-07-20 17:55:12 +08002/*
3 * Copyright (C) 2016 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
Wenyou Yang8c772bd2016-07-20 17:55:12 +08005 */
6
7#include <common.h>
8#include <clk-uclass.h>
Simon Glass11c89f32017-05-17 17:18:03 -06009#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Wenyou Yang8c772bd2016-07-20 17:55:12 +080011#include <dm/lists.h>
Heiko Stübner9a2cdca2017-02-18 19:46:21 +010012#include <dm/util.h>
Wenyou Yang8c772bd2016-07-20 17:55:12 +080013#include "pmc.h"
14
15DECLARE_GLOBAL_DATA_PTR;
16
Wenyou Yang8c772bd2016-07-20 17:55:12 +080017static const struct udevice_id at91_pmc_match[] = {
Wenyou Yang217c9682017-04-14 14:53:24 +080018 { .compatible = "atmel,at91rm9200-pmc" },
19 { .compatible = "atmel,at91sam9260-pmc" },
20 { .compatible = "atmel,at91sam9g45-pmc" },
21 { .compatible = "atmel,at91sam9n12-pmc" },
22 { .compatible = "atmel,at91sam9x5-pmc" },
23 { .compatible = "atmel,sama5d3-pmc" },
Wenyou Yang8c772bd2016-07-20 17:55:12 +080024 { .compatible = "atmel,sama5d2-pmc" },
25 {}
26};
27
Walter Lozano2901ac62020-06-25 01:10:04 -030028U_BOOT_DRIVER(atmel_at91rm9200_pmc) = {
29 .name = "atmel_at91rm9200_pmc",
Wenyou Yange4009302016-09-13 10:25:55 +080030 .id = UCLASS_SIMPLE_BUS,
Wenyou Yang8c772bd2016-07-20 17:55:12 +080031 .of_match = at91_pmc_match,
Wenyou Yang8c772bd2016-07-20 17:55:12 +080032};
33
Walter Lozano48e5b042020-06-25 01:10:06 -030034U_BOOT_DRIVER_ALIAS(atmel_at91rm9200_pmc, atmel_at91sam9260_pmc)
35
Wenyou Yang9a71d392016-09-27 11:00:29 +080036/*---------------------------------------------------------*/
37
Wenyou Yang8c772bd2016-07-20 17:55:12 +080038int at91_pmc_core_probe(struct udevice *dev)
39{
40 struct pmc_platdata *plat = dev_get_platdata(dev);
41
42 dev = dev_get_parent(dev);
43
Masahiro Yamada32822d02020-08-04 14:14:43 +090044 plat->reg_base = dev_read_addr_ptr(dev);
Wenyou Yang8c772bd2016-07-20 17:55:12 +080045
46 return 0;
47}
48
Wenyou Yang9a71d392016-09-27 11:00:29 +080049/**
50 * at91_clk_sub_device_bind() - for the at91 clock driver
51 * Recursively bind its children as clk devices.
52 *
53 * @return: 0 on success, or negative error code on failure
54 */
55int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
Wenyou Yang8c772bd2016-07-20 17:55:12 +080056{
57 const void *fdt = gd->fdt_blob;
Simon Glassdd79d6e2017-01-17 16:52:55 -070058 int offset = dev_of_offset(dev);
Wenyou Yang9a71d392016-09-27 11:00:29 +080059 bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
Wenyou Yang8c772bd2016-07-20 17:55:12 +080060 const char *name;
61 int ret;
62
63 for (offset = fdt_first_subnode(fdt, offset);
64 offset > 0;
65 offset = fdt_next_subnode(fdt, offset)) {
Wenyou Yang9a71d392016-09-27 11:00:29 +080066 if (pre_reloc_only &&
Patrick Delaunay9d0731d2020-04-03 11:39:18 +020067 !ofnode_pre_reloc(offset_to_ofnode(offset)))
Wenyou Yang9a71d392016-09-27 11:00:29 +080068 continue;
69 /*
70 * If this node has "compatible" property, this is not
71 * a clock sub-node, but a normal device. skip.
72 */
73 fdt_get_property(fdt, offset, "compatible", &ret);
74 if (ret >= 0)
75 continue;
76
77 if (ret != -FDT_ERR_NOTFOUND)
78 return ret;
79
Wenyou Yang8c772bd2016-07-20 17:55:12 +080080 name = fdt_get_name(fdt, offset, NULL);
81 if (!name)
82 return -EINVAL;
Wenyou Yang9a71d392016-09-27 11:00:29 +080083 ret = device_bind_driver_to_node(dev, drv_name, name,
Simon Glasse6dd8da2017-05-18 20:09:07 -060084 offset_to_ofnode(offset), NULL);
Wenyou Yang8c772bd2016-07-20 17:55:12 +080085 if (ret)
86 return ret;
87 }
88
89 return 0;
90}
91
Simon Glassb7ae2772017-05-18 20:09:40 -060092int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
Wenyou Yang9a71d392016-09-27 11:00:29 +080093{
94 int periph;
95
96 if (args->args_count) {
97 debug("Invalid args_count: %d\n", args->args_count);
98 return -EINVAL;
99 }
100
Simon Glassdd79d6e2017-01-17 16:52:55 -0700101 periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
102 -1);
Wenyou Yang9a71d392016-09-27 11:00:29 +0800103 if (periph < 0)
104 return -EINVAL;
105
106 clk->id = periph;
107
108 return 0;
109}
110
111int at91_clk_probe(struct udevice *dev)
112{
113 struct udevice *dev_periph_container, *dev_pmc;
114 struct pmc_platdata *plat = dev_get_platdata(dev);
115
116 dev_periph_container = dev_get_parent(dev);
117 dev_pmc = dev_get_parent(dev_periph_container);
118
Masahiro Yamada32822d02020-08-04 14:14:43 +0900119 plat->reg_base = dev_read_addr_ptr(dev_pmc);
Wenyou Yang9a71d392016-09-27 11:00:29 +0800120
121 return 0;
122}
Claudiu Beznea8fdb4252020-09-07 17:46:38 +0300123
124/**
125 * pmc_read() - read content at address base + off into val
126 *
127 * @base: base address
128 * @off: offset to read from
129 * @val: where the content of base + off is stored
130 *
131 * @return: void
132 */
133void pmc_read(void __iomem *base, unsigned int off, unsigned int *val)
134{
135 *val = readl(base + off);
136}
137
138/**
139 * pmc_write() - write content of val at address base + off
140 *
141 * @base: base address
142 * @off: offset to write to
143 * @val: content to be written at base + off
144 *
145 * @return: void
146 */
147void pmc_write(void __iomem *base, unsigned int off, unsigned int val)
148{
149 writel(val, base + off);
150}
151
152/**
153 * pmc_update_bits() - update a set of bits at address base + off
154 *
155 * @base: base address
156 * @off: offset to be updated
157 * @mask: mask of bits to be updated
158 * @bits: the new value to be updated
159 *
160 * @return: void
161 */
162void pmc_update_bits(void __iomem *base, unsigned int off,
163 unsigned int mask, unsigned int bits)
164{
165 unsigned int tmp;
166
167 tmp = readl(base + off);
168 tmp &= ~mask;
169 writel(tmp | (bits & mask), base + off);
170}
171
172/**
173 * at91_clk_mux_val_to_index() - get parent index in mux table
174 *
175 * @table: clock mux table
176 * @num_parents: clock number of parents
177 * @val: clock id who's mux index should be retrieved
178 *
179 * @return: clock index in mux table or a negative error number in case of
180 * failure
181 */
182int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val)
183{
184 int i;
185
186 if (!table || !num_parents)
187 return -EINVAL;
188
189 for (i = 0; i < num_parents; i++) {
190 if (table[i] == val)
191 return i;
192 }
193
194 return -EINVAL;
195}
196
197/**
198 * at91_clk_mux_index_to_val() - get parent ID corresponding to an entry in
199 * clock's mux table
200 *
201 * @table: clock's mux table
202 * @num_parents: clock's number of parents
203 * @index: index in mux table which clock's ID should be retrieved
204 *
205 * @return: clock ID or a negative error number in case of failure
206 */
207int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index)
208{
209 if (!table || !num_parents || index < 0 || index > num_parents)
210 return -EINVAL;
211
212 return table[index];
213}