| Patrick Rudolph | cb42bc8 | 2024-10-23 15:20:08 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (c) 2024 9elements GmbH |
| 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_H |
| 7 | #define __CONFIG_H |
| 8 | |
| 9 | /* Physical memory map */ |
| 10 | |
| 11 | /* SECURE_FLASH */ |
| 12 | #define SBSA_SECURE_FLASH_BASE_ADDR 0x00000000 |
| 13 | #define SBSA_SECURE_FLASH_LENGTH 0x10000000 |
| 14 | |
| 15 | /* FLASH */ |
| 16 | #define SBSA_FLASH_BASE_ADDR 0x10000000 |
| 17 | #define SBSA_FLASH_LENGTH 0x10000000 |
| 18 | |
| 19 | /* PERIPH */ |
| 20 | #define SBSA_PERIPH_BASE_ADDR 0x40000000 |
| 21 | |
| 22 | /* GIC_DIST */ |
| 23 | #define SBSA_GIC_DIST_BASE_ADDR 0x40060000 |
| 24 | #define SBSA_GIC_DIST_LENGTH 0x00020000 |
| 25 | |
| 26 | #define SBSA_GIC_VBASE_ADDR 0x2c020000 |
| 27 | #define SBSA_GIC_VBASE_LENGTH 0x00010000 |
| 28 | |
| 29 | #define SBSA_GIC_HBASE_ADDR 0x2c010000 |
| 30 | #define SBSA_GIC_HBASE_LENGTH 0x00010000 |
| 31 | |
| 32 | /* GIC_REDIST */ |
| 33 | #define SBSA_GIC_REDIST_BASE_ADDR 0x40080000 |
| 34 | #define SBSA_GIC_REDIST_LENGTH 0x04000000 |
| 35 | |
| 36 | /* GIC_ITS */ |
| 37 | #define SBSA_GIC_ITS_BASE_ADDR 0x44081000 |
| 38 | |
| 39 | /* UART */ |
| 40 | #define SBSA_UART_BASE_ADDR 0x60000000 |
| 41 | #define SBSA_UART_LENGTH 0x00001000 |
| 42 | |
| 43 | /* SMMU */ |
| 44 | #define SBSA_SMMU_BASE_ADDR 0x60050000 |
| 45 | |
| 46 | /* SATA */ |
| 47 | #define SBSA_AHCI_BASE_ADDR 0x60100000 |
| 48 | #define SBSA_AHCI_LENGTH 0x00010000 |
| 49 | |
| 50 | /* xHCI */ |
| 51 | #define SBSA_XHCI_BASE_ADDR 0x60110000 |
| 52 | #define SBSA_XHCI_LENGTH 0x00010000 |
| 53 | |
| 54 | /* PIO */ |
| 55 | #define SBSA_PIO_BASE_ADDR 0x7fff0000 |
| 56 | #define SBSA_PIO_LENGTH 0x00010000 |
| 57 | |
| 58 | /* PCIE_MMIO */ |
| 59 | #define SBSA_PCIE_MMIO_BASE_ADDR 0x80000000 |
| 60 | #define SBSA_PCIE_MMIO_LENGTH 0x70000000 |
| 61 | #define SBSA_PCIE_MMIO_END 0xefffffff |
| 62 | |
| 63 | /* PCIE_ECAM */ |
| 64 | #define SBSA_PCIE_ECAM_BASE_ADDR 0xf0000000 |
| 65 | #define SBSA_PCIE_ECAM_LENGTH 0x10000000 |
| 66 | #define SBSA_PCIE_ECAM_END 0xffffffff |
| 67 | |
| 68 | /* PCIE_MMIO_HIGH */ |
| 69 | #ifdef __ACPI__ |
| 70 | #define SBSA_PCIE_MMIO_HIGH_BASE_ADDR 0x100000000 |
| 71 | #define SBSA_PCIE_MMIO_HIGH_LENGTH 0xFF00000000 |
| 72 | #define SBSA_PCIE_MMIO_HIGH_END 0xFFFFFFFFFF |
| 73 | #else |
| 74 | #define SBSA_PCIE_MMIO_HIGH_BASE_ADDR 0x100000000ULL |
| 75 | #define SBSA_PCIE_MMIO_HIGH_LENGTH 0xFF00000000ULL |
| 76 | #define SBSA_PCIE_MMIO_HIGH_END 0xFFFFFFFFFFULL |
| 77 | #endif |
| 78 | |
| 79 | /* MEM */ |
| 80 | #ifdef __ACPI__ |
| 81 | #define SBSA_MEM_BASE_ADDR 0x10000000000 |
| 82 | #else |
| 83 | #define SBSA_MEM_BASE_ADDR 0x10000000000ULL |
| 84 | #endif |
| 85 | |
| 86 | #define CFG_SYS_INIT_RAM_ADDR SBSA_MEM_BASE_ADDR |
| 87 | #define CFG_SYS_INIT_RAM_SIZE 0x1000000 |
| 88 | |
| 89 | #endif /* __CONFIG_H */ |