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git01.mediatek.com / filogic / uboot / 8fbacd5bd02c3582e37ffa2924b3f372f9a80410 / . / arch / arm / dts / k3-am625-r5-sk.dts
blob: d2dd75469c1a60993556d5c999c279a7d5b91532 [file] [log] [blame]
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM625 SK dts file for R5 SPL
4 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
7#include "k3-am625-sk.dts"
8#include "k3-am62x-sk-ddr4-1600MTs.dtsi"
9#include "k3-am62-ddr.dtsi"
10
11#include "k3-am625-sk-u-boot.dtsi"
12
13/ {
14 aliases {
15 remoteproc0 = &sysctrler;
16 remoteproc1 = &a53_0;
17 serial0 = &wkup_uart0;
18 serial3 = &main_uart1;
19 };
20
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]21 a53_0: a53@0 {
22 compatible = "ti,am654-rproc";
23 reg = <0x00 0x00a90000 0x00 0x10>;
24 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhryf023d772023-04-14 09:47:59 +0530[diff] [blame]25 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
26 <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]27 resets = <&k3_reset 135 0>;
Manorit Chawdhryf23728b2024-10-15 16:22:19 +0530[diff] [blame]28 clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
29 clock-names = "gtc", "core";
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]30 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
31 assigned-clock-parents = <&k3_clks 61 2>;
32 assigned-clock-rates = <200000000>, <1200000000>;
33 ti,sci = <&dmsc>;
34 ti,sci-proc-id = <32>;
35 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]37 };
38
39 dm_tifs: dm-tifs {
40 compatible = "ti,j721e-dm-sci";
41 ti,host-id = <36>;
42 ti,secure-host;
43 mbox-names = "rx", "tx";
44 mboxes= <&secure_proxy_main 22>,
45 <&secure_proxy_main 23>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]47 };
48};
49
50&dmsc {
51 mboxes= <&secure_proxy_main 0>,
52 <&secure_proxy_main 1>,
53 <&secure_proxy_main 0>;
54 mbox-names = "rx", "tx", "notify";
55 ti,host-id = <35>;
56 ti,secure-host;
57};
58
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]59&secure_proxy_sa3 {
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]60 /* We require this for boot handshake */
61 status = "okay";
62};
63
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]64&cbass_main {
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]65 sysctrler: sysctrler {
66 compatible = "ti,am654-system-controller";
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]67 mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]68 mbox-names = "tx", "rx", "boot_notify";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]70 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]71};
72
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]73/* WKUP UART0 is used for DM firmware logs */
74&wkup_uart0 {
Nishanth Menonb26b8cf2023-11-14 21:28:57 -0600[diff] [blame]75 status = "okay";
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]76};
77
78/* Main UART1 is used for TIFS firmware logs */
79&main_uart1 {
Nishanth Menonb26b8cf2023-11-14 21:28:57 -0600[diff] [blame]80 status = "okay";
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]81};
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]82
83&ospi0 {
84 reg = <0x00 0x0fc40000 0x00 0x100>,
85 <0x00 0x60000000 0x00 0x08000000>;
86};
Siddharth Vadapallib5e87a22024-08-26 15:55:14 +0530[diff] [blame]87
88&main_pktdma {
89 ti,sci = <&dm_tifs>;
90 bootph-all;
91};