| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Paul Burton | 79ac174 | 2016-09-21 11:18:53 +0100 | [diff] [blame] | 2 | /* |
| 3 | * MIPS Coherence Manager (CM) Initialisation |
| 4 | * |
| 5 | * Copyright (c) 2016 Imagination Technologies Ltd. |
| Paul Burton | 79ac174 | 2016-09-21 11:18:53 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <asm/addrspace.h> |
| 9 | #include <asm/asm.h> |
| 10 | #include <asm/cm.h> |
| 11 | #include <asm/mipsregs.h> |
| 12 | #include <asm/regdef.h> |
| 13 | |
| 14 | LEAF(mips_cm_map) |
| 15 | /* Config3 must exist for a CM to be present */ |
| 16 | mfc0 t0, CP0_CONFIG, 1 |
| 17 | bgez t0, 2f |
| 18 | mfc0 t0, CP0_CONFIG, 2 |
| 19 | bgez t0, 2f |
| 20 | |
| 21 | /* Check Config3.CMGCR to determine CM presence */ |
| 22 | mfc0 t0, CP0_CONFIG, 3 |
| 23 | and t0, t0, MIPS_CONF3_CMGCR |
| 24 | beqz t0, 2f |
| 25 | |
| 26 | /* Find the current physical GCR base address */ |
| 27 | 1: MFC0 t0, CP0_CMGCRBASE |
| 28 | PTR_SLL t0, t0, 4 |
| 29 | |
| 30 | /* If the GCRs are where we want, we're done */ |
| 31 | PTR_LI t1, CONFIG_MIPS_CM_BASE |
| 32 | beq t0, t1, 2f |
| 33 | |
| 34 | /* Move the GCRs to our configured base address */ |
| 35 | PTR_LI t2, CKSEG1 |
| 36 | PTR_ADDU t0, t0, t2 |
| 37 | sw zero, GCR_BASE_UPPER(t0) |
| 38 | sw t1, GCR_BASE(t0) |
| 39 | |
| 40 | /* Re-check the GCR base */ |
| 41 | b 1b |
| 42 | |
| 43 | 2: jr ra |
| 44 | END(mips_cm_map) |