blob: aa159f8d41d4f336f4e56df6d1c739bab0fd98c2 [file] [log] [blame]
Jon Loeligere4773be2006-10-19 11:02:16 -05001/*
Timur Tabi2165c622009-09-04 16:28:35 -05002 * Copyright 2006,2009 Freescale Semiconductor, Inc.
Jon Loeligere4773be2006-10-19 11:02:16 -05003 *
Heiko Schocherf2850742012-10-24 13:48:22 +02004 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * Changes for multibus/multiadapter I2C support.
6 *
Jon Loeligere4773be2006-10-19 11:02:16 -05007 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * Version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
Jon Loeligere4773be2006-10-19 11:02:16 -050022#include <common.h>
Jon Loeliger24df9772006-10-19 12:02:24 -050023#include <command.h>
Jon Loeliger43d818f2006-10-20 15:50:15 -050024#include <i2c.h> /* Functional interface */
Jon Loeligere4773be2006-10-19 11:02:16 -050025#include <asm/io.h>
Jon Loeliger43d818f2006-10-20 15:50:15 -050026#include <asm/fsl_i2c.h> /* HW definitions */
Jon Loeligere4773be2006-10-19 11:02:16 -050027
Timur Tabi2165c622009-09-04 16:28:35 -050028/* The maximum number of microseconds we will wait until another master has
29 * released the bus. If not defined in the board header file, then use a
30 * generic value.
31 */
32#ifndef CONFIG_I2C_MBB_TIMEOUT
33#define CONFIG_I2C_MBB_TIMEOUT 100000
34#endif
35
36/* The maximum number of microseconds we will wait for a read or write
37 * operation to complete. If not defined in the board header file, then use a
38 * generic value.
39 */
40#ifndef CONFIG_I2C_TIMEOUT
41#define CONFIG_I2C_TIMEOUT 10000
42#endif
Jon Loeligere4773be2006-10-19 11:02:16 -050043
Joakim Tjernlundc32c5f72006-11-28 16:17:27 -060044#define I2C_READ_BIT 1
45#define I2C_WRITE_BIT 0
46
Timur Tabib301fda2008-03-14 17:45:29 -050047DECLARE_GLOBAL_DATA_PTR;
48
Timur Tabib301fda2008-03-14 17:45:29 -050049static const struct fsl_i2c *i2c_dev[2] = {
Heiko Schocherf2850742012-10-24 13:48:22 +020050 (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
51#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
52 (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET)
Timur Tabiab347542006-11-03 19:15:00 -060053#endif
54};
Jon Loeligere4773be2006-10-19 11:02:16 -050055
Timur Tabib301fda2008-03-14 17:45:29 -050056/* I2C speed map for a DFSR value of 1 */
57
58/*
59 * Map I2C frequency dividers to FDR and DFSR values
60 *
61 * This structure is used to define the elements of a table that maps I2C
62 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
63 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
64 * Sampling Rate (DFSR) registers.
65 *
66 * The actual table should be defined in the board file, and it must be called
67 * fsl_i2c_speed_map[].
68 *
69 * The last entry of the table must have a value of {-1, X}, where X is same
70 * FDR/DFSR values as the second-to-last entry. This guarantees that any
71 * search through the array will always find a match.
72 *
73 * The values of the divider must be in increasing numerical order, i.e.
74 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
75 *
76 * For this table, the values are based on a value of 1 for the DFSR
77 * register. See the application note AN2919 "Determining the I2C Frequency
78 * Divider Ratio for SCL"
TsiChung Liew00648a72008-08-19 00:56:46 +060079 *
80 * ColdFire I2C frequency dividers for FDR values are different from
81 * PowerPC. The protocol to use the I2C module is still the same.
82 * A different table is defined and are based on MCF5xxx user manual.
83 *
Timur Tabib301fda2008-03-14 17:45:29 -050084 */
85static const struct {
86 unsigned short divider;
Timur Tabib301fda2008-03-14 17:45:29 -050087 u8 fdr;
88} fsl_i2c_speed_map[] = {
Joakim Tjernlund5a6e0612009-09-17 11:07:17 +020089#ifdef __M68K__
TsiChung Liew00648a72008-08-19 00:56:46 +060090 {20, 32}, {22, 33}, {24, 34}, {26, 35},
91 {28, 0}, {28, 36}, {30, 1}, {32, 37},
92 {34, 2}, {36, 38}, {40, 3}, {40, 39},
93 {44, 4}, {48, 5}, {48, 40}, {56, 6},
94 {56, 41}, {64, 42}, {68, 7}, {72, 43},
95 {80, 8}, {80, 44}, {88, 9}, {96, 41},
96 {104, 10}, {112, 42}, {128, 11}, {128, 43},
97 {144, 12}, {160, 13}, {160, 48}, {192, 14},
98 {192, 49}, {224, 50}, {240, 15}, {256, 51},
99 {288, 16}, {320, 17}, {320, 52}, {384, 18},
100 {384, 53}, {448, 54}, {480, 19}, {512, 55},
101 {576, 20}, {640, 21}, {640, 56}, {768, 22},
102 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
103 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
104 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
105 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
106 {-1, 31}
107#endif
Timur Tabib301fda2008-03-14 17:45:29 -0500108};
109
110/**
111 * Set the I2C bus speed for a given I2C device
112 *
113 * @param dev: the I2C device
114 * @i2c_clk: I2C bus clock frequency
115 * @speed: the desired speed of the bus
116 *
117 * The I2C device must be stopped before calling this function.
118 *
119 * The return value is the actual bus speed that is set.
120 */
121static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
122 unsigned int i2c_clk, unsigned int speed)
123{
124 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
Timur Tabib301fda2008-03-14 17:45:29 -0500125
126 /*
127 * We want to choose an FDR/DFSR that generates an I2C bus speed that
128 * is equal to or lower than the requested speed. That means that we
129 * want the first divider that is equal to or greater than the
130 * calculated divider.
131 */
TsiChung Liew00648a72008-08-19 00:56:46 +0600132#ifdef __PPC__
Joakim Tjernlund5a6e0612009-09-17 11:07:17 +0200133 u8 dfsr, fdr = 0x31; /* Default if no FDR found */
134 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
135 unsigned short a, b, ga, gb;
136 unsigned long c_div, est_div;
137
Joakim Tjernlunde677e702009-09-17 11:07:16 +0200138#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
Joakim Tjernlund5a6e0612009-09-17 11:07:17 +0200139 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
Joakim Tjernlunde677e702009-09-17 11:07:16 +0200140#else
Joakim Tjernlund5a6e0612009-09-17 11:07:17 +0200141 /* Condition 1: dfsr <= 50/T */
142 dfsr = (5 * (i2c_clk / 1000)) / 100000;
Joakim Tjernlunde677e702009-09-17 11:07:16 +0200143#endif
144#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
Joakim Tjernlund5a6e0612009-09-17 11:07:17 +0200145 fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
146 speed = i2c_clk / divider; /* Fake something */
147#else
148 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
149 if (!dfsr)
150 dfsr = 1;
151
152 est_div = ~0;
153 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
154 for (gb = 0; gb < 8; gb++) {
155 b = 16 << gb;
156 c_div = b * (a + ((3*dfsr)/b)*2);
157 if ((c_div > divider) && (c_div < est_div)) {
158 unsigned short bin_gb, bin_ga;
159
160 est_div = c_div;
161 bin_gb = gb << 2;
162 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
163 fdr = bin_gb | bin_ga;
164 speed = i2c_clk / est_div;
165 debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
166 "a:%d, b:%d, speed:%d\n",
167 fdr, est_div, ga, gb, a, b, speed);
168 /* Condition 2 not accounted for */
169 debug("Tr <= %d ns\n",
170 (b - 3 * dfsr) * 1000000 /
171 (i2c_clk / 1000));
172 }
173 }
174 if (a == 20)
175 a += 2;
176 if (a == 24)
177 a += 4;
178 }
179 debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
180 debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
181#endif
182 writeb(dfsr, &dev->dfsrr); /* set default filter */
183 writeb(fdr, &dev->fdr); /* set bus speed */
Joakim Tjernlunde677e702009-09-17 11:07:16 +0200184#else
Joakim Tjernlund5a6e0612009-09-17 11:07:17 +0200185 unsigned int i;
186
187 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
188 if (fsl_i2c_speed_map[i].divider >= divider) {
189 u8 fdr;
190
Timur Tabib301fda2008-03-14 17:45:29 -0500191 fdr = fsl_i2c_speed_map[i].fdr;
192 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
Joakim Tjernlunde677e702009-09-17 11:07:16 +0200193 writeb(fdr, &dev->fdr); /* set bus speed */
194
Timur Tabib301fda2008-03-14 17:45:29 -0500195 break;
196 }
Joakim Tjernlund5a6e0612009-09-17 11:07:17 +0200197#endif
Timur Tabib301fda2008-03-14 17:45:29 -0500198 return speed;
199}
200
Kim Phillipsdd018632012-10-16 14:28:43 +0000201static unsigned int get_i2c_clock(int bus)
Jerry Huang5e015612011-10-26 15:29:38 +0000202{
203 if (bus)
Simon Glassc2baaec2012-12-13 20:48:49 +0000204 return gd->arch.i2c2_clk; /* I2C2 clock */
Jerry Huang5e015612011-10-26 15:29:38 +0000205 else
Simon Glassc2baaec2012-12-13 20:48:49 +0000206 return gd->arch.i2c1_clk; /* I2C1 clock */
Jerry Huang5e015612011-10-26 15:29:38 +0000207}
208
Chunhe Lan2e13d572013-08-16 15:10:36 +0800209static int fsl_i2c_fixup(const struct fsl_i2c *dev)
210{
211 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
212 unsigned long long timeval = 0;
213 int ret = -1;
Chunhe Lan92546402013-08-16 15:10:37 +0800214 unsigned int flags = 0;
215
216#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
217 unsigned int svr = get_svr();
218 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
219 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
220 flags = I2C_CR_BIT6;
221#endif
Chunhe Lan2e13d572013-08-16 15:10:36 +0800222
223 writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr);
224
225 timeval = get_ticks();
226 while (!(readb(&dev->sr) & I2C_SR_MBB)) {
227 if ((get_ticks() - timeval) > timeout)
228 goto err;
229 }
230
231 if (readb(&dev->sr) & I2C_SR_MAL) {
232 /* SDA is stuck low */
233 writeb(0, &dev->cr);
234 udelay(100);
Chunhe Lan92546402013-08-16 15:10:37 +0800235 writeb(I2C_CR_MSTA | flags, &dev->cr);
236 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr);
Chunhe Lan2e13d572013-08-16 15:10:36 +0800237 }
238
239 readb(&dev->dr);
240
241 timeval = get_ticks();
242 while (!(readb(&dev->sr) & I2C_SR_MIF)) {
243 if ((get_ticks() - timeval) > timeout)
244 goto err;
245 }
246 ret = 0;
247
248err:
Chunhe Lan92546402013-08-16 15:10:37 +0800249 writeb(I2C_CR_MEN | flags, &dev->cr);
Chunhe Lan2e13d572013-08-16 15:10:36 +0800250 writeb(0, &dev->sr);
251 udelay(100);
252
253 return ret;
254}
255
Heiko Schocherf2850742012-10-24 13:48:22 +0200256static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
Jon Loeligere4773be2006-10-19 11:02:16 -0500257{
Kumar Gala4e506ca2011-11-08 03:39:43 +0000258 const struct fsl_i2c *dev;
Chunhe Lan2e13d572013-08-16 15:10:36 +0800259 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
260 unsigned long long timeval;
Jon Loeligere4773be2006-10-19 11:02:16 -0500261
Heiko Schocherc5ca01f2009-07-09 12:04:26 +0200262#ifdef CONFIG_SYS_I2C_INIT_BOARD
Richard Retanubundf0149c2010-04-12 15:08:17 -0400263 /* Call board specific i2c bus reset routine before accessing the
264 * environment, which might be in a chip on that bus. For details
265 * about this problem see doc/I2C_Edge_Conditions.
266 */
Heiko Schocherc5ca01f2009-07-09 12:04:26 +0200267 i2c_init_board();
268#endif
Heiko Schocherf2850742012-10-24 13:48:22 +0200269 dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Jerry Huang5e015612011-10-26 15:29:38 +0000270
Heiko Schocherf2850742012-10-24 13:48:22 +0200271 writeb(0, &dev->cr); /* stop I2C controller */
272 udelay(5); /* let it shutdown in peace */
273 set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
274 writeb(slaveadd << 1, &dev->adr);/* write slave address */
275 writeb(0x0, &dev->sr); /* clear status register */
276 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
Richard Retanubundf0149c2010-04-12 15:08:17 -0400277
Chunhe Lan2e13d572013-08-16 15:10:36 +0800278 timeval = get_ticks();
279 while (readb(&dev->sr) & I2C_SR_MBB) {
280 if ((get_ticks() - timeval) < timeout)
281 continue;
282
283 if (fsl_i2c_fixup(dev))
284 debug("i2c_init: BUS#%d failed to init\n",
285 adap->hwadapnr);
286
287 break;
288 }
289
Richard Retanubundf0149c2010-04-12 15:08:17 -0400290#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
291 /* Call board specific i2c bus reset routine AFTER the bus has been
292 * initialized. Use either this callpoint or i2c_init_board;
293 * which is called before i2c_init operations.
294 * For details about this problem see doc/I2C_Edge_Conditions.
295 */
296 i2c_board_late_init();
297#endif
Jon Loeligere4773be2006-10-19 11:02:16 -0500298}
299
Joakim Tjernlundc324b782009-09-17 11:07:15 +0200300static int
Heiko Schocherf2850742012-10-24 13:48:22 +0200301i2c_wait4bus(struct i2c_adapter *adap)
Jon Loeligere4773be2006-10-19 11:02:16 -0500302{
Heiko Schocherf2850742012-10-24 13:48:22 +0200303 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Stefan Roese37628252008-08-06 14:05:38 +0200304 unsigned long long timeval = get_ticks();
Timur Tabi2165c622009-09-04 16:28:35 -0500305 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
Jon Loeligere4773be2006-10-19 11:02:16 -0500306
Heiko Schocherf2850742012-10-24 13:48:22 +0200307 while (readb(&dev->sr) & I2C_SR_MBB) {
Timur Tabi2165c622009-09-04 16:28:35 -0500308 if ((get_ticks() - timeval) > timeout)
Jon Loeligere4773be2006-10-19 11:02:16 -0500309 return -1;
Jon Loeligere4773be2006-10-19 11:02:16 -0500310 }
311
312 return 0;
313}
314
315static __inline__ int
Heiko Schocherf2850742012-10-24 13:48:22 +0200316i2c_wait(struct i2c_adapter *adap, int write)
Jon Loeligere4773be2006-10-19 11:02:16 -0500317{
318 u32 csr;
Stefan Roese37628252008-08-06 14:05:38 +0200319 unsigned long long timeval = get_ticks();
Timur Tabi2165c622009-09-04 16:28:35 -0500320 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
Heiko Schocherf2850742012-10-24 13:48:22 +0200321 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Jon Loeligere4773be2006-10-19 11:02:16 -0500322
323 do {
Heiko Schocherf2850742012-10-24 13:48:22 +0200324 csr = readb(&dev->sr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500325 if (!(csr & I2C_SR_MIF))
326 continue;
Joakim Tjernlundc324b782009-09-17 11:07:15 +0200327 /* Read again to allow register to stabilise */
Heiko Schocherf2850742012-10-24 13:48:22 +0200328 csr = readb(&dev->sr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500329
Heiko Schocherf2850742012-10-24 13:48:22 +0200330 writeb(0x0, &dev->sr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500331
332 if (csr & I2C_SR_MAL) {
333 debug("i2c_wait: MAL\n");
334 return -1;
335 }
336
337 if (!(csr & I2C_SR_MCF)) {
338 debug("i2c_wait: unfinished\n");
339 return -1;
340 }
341
Joakim Tjernlundc32c5f72006-11-28 16:17:27 -0600342 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
Jon Loeligere4773be2006-10-19 11:02:16 -0500343 debug("i2c_wait: No RXACK\n");
344 return -1;
345 }
346
347 return 0;
Timur Tabi2165c622009-09-04 16:28:35 -0500348 } while ((get_ticks() - timeval) < timeout);
Jon Loeligere4773be2006-10-19 11:02:16 -0500349
350 debug("i2c_wait: timed out\n");
351 return -1;
352}
353
354static __inline__ int
Heiko Schocherf2850742012-10-24 13:48:22 +0200355i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
Jon Loeligere4773be2006-10-19 11:02:16 -0500356{
Heiko Schocherf2850742012-10-24 13:48:22 +0200357 struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
358
Jon Loeligere4773be2006-10-19 11:02:16 -0500359 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
360 | (rsta ? I2C_CR_RSTA : 0),
Heiko Schocherf2850742012-10-24 13:48:22 +0200361 &device->cr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500362
Heiko Schocherf2850742012-10-24 13:48:22 +0200363 writeb((dev << 1) | dir, &device->dr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500364
Heiko Schocherf2850742012-10-24 13:48:22 +0200365 if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
Jon Loeligere4773be2006-10-19 11:02:16 -0500366 return 0;
367
368 return 1;
369}
370
371static __inline__ int
Heiko Schocherf2850742012-10-24 13:48:22 +0200372__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
Jon Loeligere4773be2006-10-19 11:02:16 -0500373{
Heiko Schocherf2850742012-10-24 13:48:22 +0200374 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Jon Loeligere4773be2006-10-19 11:02:16 -0500375 int i;
376
Jon Loeligere4773be2006-10-19 11:02:16 -0500377 for (i = 0; i < length; i++) {
Heiko Schocherf2850742012-10-24 13:48:22 +0200378 writeb(data[i], &dev->dr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500379
Heiko Schocherf2850742012-10-24 13:48:22 +0200380 if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
Jon Loeligere4773be2006-10-19 11:02:16 -0500381 break;
382 }
383
384 return i;
385}
386
387static __inline__ int
Heiko Schocherf2850742012-10-24 13:48:22 +0200388__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
Jon Loeligere4773be2006-10-19 11:02:16 -0500389{
Heiko Schocherf2850742012-10-24 13:48:22 +0200390 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Jon Loeligere4773be2006-10-19 11:02:16 -0500391 int i;
392
393 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
Heiko Schocherf2850742012-10-24 13:48:22 +0200394 &dev->cr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500395
396 /* dummy read */
Heiko Schocherf2850742012-10-24 13:48:22 +0200397 readb(&dev->dr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500398
399 for (i = 0; i < length; i++) {
Heiko Schocherf2850742012-10-24 13:48:22 +0200400 if (i2c_wait(adap, I2C_READ_BIT) < 0)
Jon Loeligere4773be2006-10-19 11:02:16 -0500401 break;
402
403 /* Generate ack on last next to last byte */
404 if (i == length - 2)
405 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
Heiko Schocherf2850742012-10-24 13:48:22 +0200406 &dev->cr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500407
Joakim Tjernlund6384da22009-09-22 13:40:44 +0200408 /* Do not generate stop on last byte */
Jon Loeligere4773be2006-10-19 11:02:16 -0500409 if (i == length - 1)
Joakim Tjernlund6384da22009-09-22 13:40:44 +0200410 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
Heiko Schocherf2850742012-10-24 13:48:22 +0200411 &dev->cr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500412
Heiko Schocherf2850742012-10-24 13:48:22 +0200413 data[i] = readb(&dev->dr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500414 }
415
416 return i;
417}
418
Heiko Schocherf2850742012-10-24 13:48:22 +0200419static int
420fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
421 int length)
Jon Loeligere4773be2006-10-19 11:02:16 -0500422{
Heiko Schocherf2850742012-10-24 13:48:22 +0200423 struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Joakim Tjernlundb648fe72007-01-31 11:04:19 +0100424 int i = -1; /* signal error */
Jon Loeligere4773be2006-10-19 11:02:16 -0500425 u8 *a = (u8*)&addr;
Shaveta Leekhafdd7efe2014-04-24 14:51:23 +0530426 int len = alen * -1;
Jon Loeligere4773be2006-10-19 11:02:16 -0500427
Heiko Schocherf2850742012-10-24 13:48:22 +0200428 if (i2c_wait4bus(adap) < 0)
Reinhard Pfau2d878de2013-06-26 15:55:14 +0200429 return -1;
430
Shaveta Leekhafdd7efe2014-04-24 14:51:23 +0530431 /* To handle the need of I2C devices that require to write few bytes
432 * (more than 4 bytes of address as in the case of else part)
433 * of data before reading, Negative equivalent of length(bytes to write)
434 * is passed, but used the +ve part of len for writing data
435 */
436 if (alen < 0) {
437 /* Generate a START and send the Address and
438 * the Tx Bytes to the slave.
439 * "START: Address: Write bytes data[len]"
440 * IF part supports writing any number of bytes in contrast
441 * to the else part, which supports writing address offset
442 * of upto 4 bytes only.
443 * bytes that need to be written are passed in
444 * "data", which will eventually keep the data READ,
445 * after writing the len bytes out of it
446 */
447 if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
448 i = __i2c_write(adap, data, len);
449
450 if (i != len)
451 return -1;
452
453 if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
454 i = __i2c_read(adap, data, length);
455 } else {
456 if ((!length || alen > 0) &&
457 i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
458 __i2c_write(adap, &a[4 - alen], alen) == alen)
459 i = 0; /* No error so far */
Joakim Tjernlundb648fe72007-01-31 11:04:19 +0100460
Shaveta Leekhafdd7efe2014-04-24 14:51:23 +0530461 if (length &&
462 i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
463 i = __i2c_read(adap, data, length);
464 }
Jon Loeligere4773be2006-10-19 11:02:16 -0500465
Heiko Schocherf2850742012-10-24 13:48:22 +0200466 writeb(I2C_CR_MEN, &device->cr);
Jon Loeligere4773be2006-10-19 11:02:16 -0500467
Heiko Schocherf2850742012-10-24 13:48:22 +0200468 if (i2c_wait4bus(adap)) /* Wait until STOP */
Joakim Tjernlund6384da22009-09-22 13:40:44 +0200469 debug("i2c_read: wait4bus timed out\n");
470
Jon Loeliger24df9772006-10-19 12:02:24 -0500471 if (i == length)
472 return 0;
473
474 return -1;
Jon Loeligere4773be2006-10-19 11:02:16 -0500475}
476
Heiko Schocherf2850742012-10-24 13:48:22 +0200477static int
478fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
479 u8 *data, int length)
Jon Loeligere4773be2006-10-19 11:02:16 -0500480{
Heiko Schocherf2850742012-10-24 13:48:22 +0200481 struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Joakim Tjernlundb648fe72007-01-31 11:04:19 +0100482 int i = -1; /* signal error */
Jon Loeligere4773be2006-10-19 11:02:16 -0500483 u8 *a = (u8*)&addr;
484
Chunhe Lan2e13d572013-08-16 15:10:36 +0800485 if (i2c_wait4bus(adap) < 0)
486 return -1;
487
488 if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
Heiko Schocherf2850742012-10-24 13:48:22 +0200489 __i2c_write(adap, &a[4 - alen], alen) == alen) {
490 i = __i2c_write(adap, data, length);
Jon Loeliger24df9772006-10-19 12:02:24 -0500491 }
Jon Loeligere4773be2006-10-19 11:02:16 -0500492
Heiko Schocherf2850742012-10-24 13:48:22 +0200493 writeb(I2C_CR_MEN, &device->cr);
494 if (i2c_wait4bus(adap)) /* Wait until STOP */
Joakim Tjernlundc324b782009-09-17 11:07:15 +0200495 debug("i2c_write: wait4bus timed out\n");
Jon Loeligere4773be2006-10-19 11:02:16 -0500496
Jon Loeliger24df9772006-10-19 12:02:24 -0500497 if (i == length)
498 return 0;
499
500 return -1;
Jon Loeligere4773be2006-10-19 11:02:16 -0500501}
502
Heiko Schocherf2850742012-10-24 13:48:22 +0200503static int
504fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
Jon Loeligere4773be2006-10-19 11:02:16 -0500505{
Heiko Schocherf2850742012-10-24 13:48:22 +0200506 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Joakim Tjernlundb648fe72007-01-31 11:04:19 +0100507 /* For unknow reason the controller will ACK when
508 * probing for a slave with the same address, so skip
509 * it.
Jon Loeligere4773be2006-10-19 11:02:16 -0500510 */
Heiko Schocherf2850742012-10-24 13:48:22 +0200511 if (chip == (readb(&dev->adr) >> 1))
Timur Tabiab347542006-11-03 19:15:00 -0600512 return -1;
Timur Tabiab347542006-11-03 19:15:00 -0600513
Heiko Schocherf2850742012-10-24 13:48:22 +0200514 return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
Timur Tabiab347542006-11-03 19:15:00 -0600515}
516
Heiko Schocherf2850742012-10-24 13:48:22 +0200517static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
518 unsigned int speed)
Timur Tabiab347542006-11-03 19:15:00 -0600519{
Heiko Schocherf2850742012-10-24 13:48:22 +0200520 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Timur Tabib301fda2008-03-14 17:45:29 -0500521
Heiko Schocherf2850742012-10-24 13:48:22 +0200522 writeb(0, &dev->cr); /* stop controller */
523 set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
524 writeb(I2C_CR_MEN, &dev->cr); /* start controller */
Timur Tabib301fda2008-03-14 17:45:29 -0500525
526 return 0;
Timur Tabiab347542006-11-03 19:15:00 -0600527}
528
Heiko Schocherf2850742012-10-24 13:48:22 +0200529/*
530 * Register fsl i2c adapters
531 */
532U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
533 fsl_i2c_write, fsl_i2c_set_bus_speed,
534 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
535 0)
536#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
537U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
538 fsl_i2c_write, fsl_i2c_set_bus_speed,
539 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
540 1)
Heiko Schocher2c9f3a42009-02-24 11:30:37 +0100541#endif