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wdenk914be132004-06-08 00:22:43 +00001/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2003
5 * Texas Instruments, <www.ti.com>
6 * Kshitij Gupta <Kshitij@ti.com>
7 *
8 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
9 *
10 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenk914be132004-06-08 00:22:43 +000012 */
13
14#include <config.h>
15#include <version.h>
16
17#if defined(CONFIG_OMAP1610)
18#include <./configs/omap1510.h>
19#endif
20
Wolfgang Denk7f88a5e2005-10-06 17:08:18 +020021.globl lowlevel_init
22lowlevel_init:
wdenk914be132004-06-08 00:22:43 +000023
Stefan Roese0df367f2006-05-10 10:55:16 +020024 /*------------------------------------------------------*
25 * Ensure i-cache is enabled *
26 * To configure TC regs without fetching instruction *
27 *------------------------------------------------------*/
28 mrc p15, 0, r0, c1, c0
29 orr r0, r0, #0x1000
30 mcr p15, 0, r0, c1, c0
wdenk914be132004-06-08 00:22:43 +000031
32 /*------------------------------------------------------*
33 *mask all IRQs by setting all bits in the INTMR default*
34 *------------------------------------------------------*/
35 mov r1, #0xffffffff
36 ldr r0, =REG_IHL1_MIR
37 str r1, [r0]
38 ldr r0, =REG_IHL2_MIR
39 str r1, [r0]
40
41 /*------------------------------------------------------*
42 * Set up ARM CLM registers (IDLECT1) *
43 *------------------------------------------------------*/
44 ldr r0, REG_ARM_IDLECT1
45 ldr r1, VAL_ARM_IDLECT1
46 str r1, [r0]
47
48 /*------------------------------------------------------*
Stefan Roese0df367f2006-05-10 10:55:16 +020049 * Set up ARM CLM registers (IDLECT2) *
wdenk914be132004-06-08 00:22:43 +000050 *------------------------------------------------------*/
51 ldr r0, REG_ARM_IDLECT2
52 ldr r1, VAL_ARM_IDLECT2
53 str r1, [r0]
54
55 /*------------------------------------------------------*
Stefan Roese0df367f2006-05-10 10:55:16 +020056 * Set up ARM CLM registers (IDLECT3) *
wdenk914be132004-06-08 00:22:43 +000057 *------------------------------------------------------*/
58 ldr r0, REG_ARM_IDLECT3
59 ldr r1, VAL_ARM_IDLECT3
60 str r1, [r0]
61
Stefan Roese0df367f2006-05-10 10:55:16 +020062 mov r1, #0x01 /* PER_EN bit */
wdenk914be132004-06-08 00:22:43 +000063 ldr r0, REG_ARM_RSTCT2
Stefan Roese0df367f2006-05-10 10:55:16 +020064 strh r1, [r0] /* CLKM; Peripheral reset. */
wdenk914be132004-06-08 00:22:43 +000065
Stefan Roese0df367f2006-05-10 10:55:16 +020066 /* Set CLKM to Sync-Scalable */
67 mov r1, #0x1000
wdenk914be132004-06-08 00:22:43 +000068 ldr r0, REG_ARM_SYSST
Stefan Roese0df367f2006-05-10 10:55:16 +020069
70 mov r2, #0
711: cmp r2, #1
72 streqh r1, [r0]
73 add r2, r2, #1
74 cmp r2, #0x100 /* wait for any bubbles to finish */
wdenk914be132004-06-08 00:22:43 +000075 bne 1b
Stefan Roese0df367f2006-05-10 10:55:16 +020076
wdenk914be132004-06-08 00:22:43 +000077 ldr r1, VAL_ARM_CKCTL
78 ldr r0, REG_ARM_CKCTL
79 strh r1, [r0]
80
81 /* a few nops to let settle */
82 nop
83 nop
84 nop
85 nop
86 nop
87 nop
88 nop
89 nop
90 nop
91 nop
92
93 /* setup DPLL 1 */
94 /* Ramp up the clock to 96Mhz */
95 ldr r1, VAL_DPLL1_CTL
96 ldr r0, REG_DPLL1_CTL
97 strh r1, [r0]
Stefan Roese0df367f2006-05-10 10:55:16 +020098 ands r1, r1, #0x10 /* Check if PLL is enabled. */
99 beq lock_end /* Do not look for lock if BYPASS selected */
wdenk914be132004-06-08 00:22:43 +00001002:
101 ldrh r1, [r0]
Stefan Roese0df367f2006-05-10 10:55:16 +0200102 ands r1, r1, #0x01 /* Check the LOCK bit.*/
103 beq 2b /* loop until bit goes hi. */
wdenk914be132004-06-08 00:22:43 +0000104lock_end:
105
wdenk914be132004-06-08 00:22:43 +0000106 /*------------------------------------------------------*
Stefan Roese0df367f2006-05-10 10:55:16 +0200107 * Turn off the watchdog during init... *
Wolfgang Denka1be4762008-05-20 16:00:29 +0200108 *------------------------------------------------------*/
wdenk914be132004-06-08 00:22:43 +0000109 ldr r0, REG_WATCHDOG
110 ldr r1, WATCHDOG_VAL1
111 str r1, [r0]
112 ldr r1, WATCHDOG_VAL2
113 str r1, [r0]
114 ldr r0, REG_WSPRDOG
115 ldr r1, WSPRDOG_VAL1
116 str r1, [r0]
117 ldr r0, REG_WWPSDOG
118
119watch1Wait:
120 ldr r1, [r0]
121 tst r1, #0x10
122 bne watch1Wait
123
124 ldr r0, REG_WSPRDOG
125 ldr r1, WSPRDOG_VAL2
126 str r1, [r0]
127 ldr r0, REG_WWPSDOG
128watch2Wait:
129 ldr r1, [r0]
130 tst r1, #0x10
131 bne watch2Wait
132
wdenk914be132004-06-08 00:22:43 +0000133 /* Set memory timings corresponding to the new clock speed */
Stefan Roese0df367f2006-05-10 10:55:16 +0200134 ldr r3, VAL_SDRAM_CONFIG_SDF0
wdenk914be132004-06-08 00:22:43 +0000135
136 /* Check execution location to determine current execution location
137 * and branch to appropriate initialization code.
138 */
Stefan Roese0df367f2006-05-10 10:55:16 +0200139 mov r0, #0x10000000 /* Load physical SDRAM base. */
140 mov r1, pc /* Get current execution location. */
141 cmp r1, r0 /* Compare. */
142 bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
143
144 /* identify the device revision, -- TMX or TMP(TMS) */
145 ldr r0, REG_DEVICE_ID
146 ldr r1, [r0]
147
148 ldr r0, VAL_DEVICE_ID_TMP
149 mov r1, r1, lsl #15
150 mov r1, r1, lsr #16
151 cmp r0, r1
152 bne skip_TMP_Patch
153
154 /* Enable TMP/TMS device new features */
155 mov r0, #1
156 ldr r1, REG_TC_EMIFF_DOUBLER
157 str r0, [r1]
158
159 /* Enable new ac parameters */
160 mov r0, #0x0b
161 ldr r1, REG_SDRAM_CONFIG2
162 str r0, [r1]
163
164 ldr r3, VAL_SDRAM_CONFIG_SDF1
165
166skip_TMP_Patch:
wdenk914be132004-06-08 00:22:43 +0000167
168 /*
169 * Delay for SDRAM initialization.
170 */
Stefan Roese0df367f2006-05-10 10:55:16 +0200171 mov r0, #0x1800 /* value should be checked */
wdenk914be132004-06-08 00:22:43 +00001723:
Stefan Roese0df367f2006-05-10 10:55:16 +0200173 subs r0, r0, #0x1 /* Decrement count */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200174 bne 3b
wdenk914be132004-06-08 00:22:43 +0000175
wdenk914be132004-06-08 00:22:43 +0000176 /*
177 * Set SDRAM control values. Disable refresh before MRS command.
178 */
179
180 /* mobile ddr operation */
181 ldr r0, REG_SDRAM_OPERATION
182 mov r2, #07
183 str r2, [r0]
184
185 /* config register */
186 ldr r0, REG_SDRAM_CONFIG
Stefan Roese0df367f2006-05-10 10:55:16 +0200187 str r3, [r0]
wdenk914be132004-06-08 00:22:43 +0000188
189 /* manual command register */
190 ldr r0, REG_SDRAM_MANUAL_CMD
Stefan Roese0df367f2006-05-10 10:55:16 +0200191
wdenk914be132004-06-08 00:22:43 +0000192 /* issue set cke high */
193 mov r1, #CMD_SDRAM_CKE_SET_HIGH
194 str r1, [r0]
Stefan Roese0df367f2006-05-10 10:55:16 +0200195
wdenk914be132004-06-08 00:22:43 +0000196 /* issue nop */
197 mov r1, #CMD_SDRAM_NOP
198 str r1, [r0]
199
200 mov r2, #0x0100
201waitMDDR1:
202 subs r2, r2, #1
203 bne waitMDDR1 /* delay loop */
204
205 /* issue precharge */
206 mov r1, #CMD_SDRAM_PRECHARGE
207 str r1, [r0]
208
209 /* issue autorefresh x 2 */
210 mov r1, #CMD_SDRAM_AUTOREFRESH
211 str r1, [r0]
212 str r1, [r0]
213
214 /* mrs register ddr mobile */
215 ldr r0, REG_SDRAM_MRS
216 mov r1, #0x33
217 str r1, [r0]
218
219 /* emrs1 low-power register */
220 ldr r0, REG_SDRAM_EMRS1
221 /* self refresh on all banks */
222 mov r1, #0
223 str r1, [r0]
224
225 ldr r0, REG_DLL_URD_CONTROL
226 ldr r1, DLL_URD_CONTROL_VAL
227 str r1, [r0]
228
229 ldr r0, REG_DLL_LRD_CONTROL
230 ldr r1, DLL_LRD_CONTROL_VAL
231 str r1, [r0]
232
233 ldr r0, REG_DLL_WRT_CONTROL
234 ldr r1, DLL_WRT_CONTROL_VAL
235 str r1, [r0]
236
237 /* delay loop */
Stefan Roese0df367f2006-05-10 10:55:16 +0200238 mov r0, #0x0100
wdenk914be132004-06-08 00:22:43 +0000239waitMDDR2:
Stefan Roese0df367f2006-05-10 10:55:16 +0200240 subs r0, r0, #1
wdenk914be132004-06-08 00:22:43 +0000241 bne waitMDDR2
242
243 /*
244 * Delay for SDRAM initialization.
245 */
Stefan Roese0df367f2006-05-10 10:55:16 +0200246 mov r0, #0x1800
wdenk914be132004-06-08 00:22:43 +00002474:
Stefan Roese0df367f2006-05-10 10:55:16 +0200248 subs r0, r0, #1 /* Decrement count. */
wdenk914be132004-06-08 00:22:43 +0000249 bne 4b
250 b common_tc
251
252skip_sdram:
wdenk914be132004-06-08 00:22:43 +0000253 ldr r0, REG_SDRAM_CONFIG
Stefan Roese0df367f2006-05-10 10:55:16 +0200254 str r3, [r0]
wdenk914be132004-06-08 00:22:43 +0000255
256common_tc:
257 /* slow interface */
258 ldr r1, VAL_TC_EMIFS_CS0_CONFIG
259 ldr r0, REG_TC_EMIFS_CS0_CONFIG
260 str r1, [r0] /* Chip Select 0 */
261
262 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
263 ldr r0, REG_TC_EMIFS_CS1_CONFIG
264 str r1, [r0] /* Chip Select 1 */
Stefan Roese0df367f2006-05-10 10:55:16 +0200265
wdenk914be132004-06-08 00:22:43 +0000266 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
267 ldr r0, REG_TC_EMIFS_CS3_CONFIG
268 str r1, [r0] /* Chip Select 3 */
269
Stefan Roese0df367f2006-05-10 10:55:16 +0200270 ldr r1, VAL_TC_EMIFS_DWS
271 ldr r0, REG_TC_EMIFS_DWS
272 str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */
273
wdenk914be132004-06-08 00:22:43 +0000274#ifdef CONFIG_H2_OMAP1610
275 /* inserting additional 2 clock cycle hold time for LAN */
276 ldr r0, REG_TC_EMIFS_CS1_ADVANCED
Wolfgang Denka1be4762008-05-20 16:00:29 +0200277 ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
wdenk914be132004-06-08 00:22:43 +0000278 str r1, [r0]
279#endif
280 /* Start MPU Timer 1 */
281 ldr r0, REG_MPU_LOAD_TIMER
282 ldr r1, VAL_MPU_LOAD_TIMER
283 str r1, [r0]
284
285 ldr r0, REG_MPU_CNTL_TIMER
286 ldr r1, VAL_MPU_CNTL_TIMER
287 str r1, [r0]
288
Jon Hunterea3814a2013-04-09 16:41:31 -0500289 /*
290 * Setup a temporary stack
291 */
292 ldr sp, SRAM_STACK
293 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
294
295 /*
296 * Save the old lr(passed in ip) and the current lr to stack
297 */
298 push {ip, lr}
299
300 /*
301 * go setup pll, mux, memory
302 */
303 bl s_init
304 pop {ip, pc}
305
wdenk914be132004-06-08 00:22:43 +0000306 /* back to arch calling code */
307 mov pc, lr
308
309 /* the literal pools origin */
310 .ltorg
311
Stefan Roese0df367f2006-05-10 10:55:16 +0200312REG_DEVICE_ID: /* 32 bits */
313 .word 0xfffe2004
314REG_TC_EMIFS_CONFIG:
wdenk914be132004-06-08 00:22:43 +0000315 .word 0xfffecc0c
316REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
317 .word 0xfffecc10
318REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
319 .word 0xfffecc14
320REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
321 .word 0xfffecc18
322REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
323 .word 0xfffecc1c
Stefan Roese0df367f2006-05-10 10:55:16 +0200324REG_TC_EMIFS_DWS: /* 32 bits */
325 .word 0xfffecc40
wdenk914be132004-06-08 00:22:43 +0000326#ifdef CONFIG_H2_OMAP1610
327REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
328 .word 0xfffecc54
329#endif
330
331/* MPU clock/reset/power mode control registers */
332REG_ARM_CKCTL: /* 16 bits */
333 .word 0xfffece00
wdenk914be132004-06-08 00:22:43 +0000334REG_ARM_IDLECT3: /* 16 bits */
335 .word 0xfffece24
336REG_ARM_IDLECT2: /* 16 bits */
337 .word 0xfffece08
338REG_ARM_IDLECT1: /* 16 bits */
339 .word 0xfffece04
wdenk914be132004-06-08 00:22:43 +0000340REG_ARM_RSTCT2: /* 16 bits */
341 .word 0xfffece14
342REG_ARM_SYSST: /* 16 bits */
343 .word 0xfffece18
Stefan Roese0df367f2006-05-10 10:55:16 +0200344
wdenk914be132004-06-08 00:22:43 +0000345/* DPLL control registers */
346REG_DPLL1_CTL: /* 16 bits */
347 .word 0xfffecf00
348
349/* Watch Dog register */
350/* secure watchdog stop */
351REG_WSPRDOG:
352 .word 0xfffeb048
353/* watchdog write pending */
354REG_WWPSDOG:
355 .word 0xfffeb034
356
357WSPRDOG_VAL1:
358 .word 0x0000aaaa
359WSPRDOG_VAL2:
360 .word 0x00005555
361
362/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
363 counter @8192 rows, 10 ns, 8 burst */
364REG_SDRAM_CONFIG:
365 .word 0xfffecc20
Stefan Roese0df367f2006-05-10 10:55:16 +0200366REG_SDRAM_CONFIG2:
367 .word 0xfffecc3c
368REG_TC_EMIFF_DOUBLER: /* 32 bits */
369 .word 0xfffecc60
wdenk914be132004-06-08 00:22:43 +0000370
371/* Operation register */
372REG_SDRAM_OPERATION:
373 .word 0xfffecc80
374
375/* Manual command register */
376REG_SDRAM_MANUAL_CMD:
377 .word 0xfffecc84
378
379/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
380REG_SDRAM_MRS:
381 .word 0xfffecc70
382
383/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
384REG_SDRAM_EMRS1:
385 .word 0xfffecc78
386
387/* WRT DLL register */
388REG_DLL_WRT_CONTROL:
389 .word 0xfffecc68
390DLL_WRT_CONTROL_VAL:
Stefan Roese0df367f2006-05-10 10:55:16 +0200391 .word 0x03f00002 /* Phase of 72deg, write offset +31 */
wdenk914be132004-06-08 00:22:43 +0000392
393/* URD DLL register */
394REG_DLL_URD_CONTROL:
395 .word 0xfffeccc0
396DLL_URD_CONTROL_VAL:
Stefan Roese0df367f2006-05-10 10:55:16 +0200397 .word 0x00800002 /* Phase of 72deg, read offset +31 */
wdenk914be132004-06-08 00:22:43 +0000398
399/* LRD DLL register */
400REG_DLL_LRD_CONTROL:
401 .word 0xfffecccc
Stefan Roese0df367f2006-05-10 10:55:16 +0200402DLL_LRD_CONTROL_VAL:
403 .word 0x00800002 /* read offset +31 */
wdenk914be132004-06-08 00:22:43 +0000404
405REG_WATCHDOG:
406 .word 0xfffec808
Stefan Roese0df367f2006-05-10 10:55:16 +0200407WATCHDOG_VAL1:
408 .word 0x000000f5
409WATCHDOG_VAL2:
410 .word 0x000000a0
wdenk914be132004-06-08 00:22:43 +0000411
412REG_MPU_LOAD_TIMER:
Stefan Roese0df367f2006-05-10 10:55:16 +0200413 .word 0xfffec504
wdenk914be132004-06-08 00:22:43 +0000414REG_MPU_CNTL_TIMER:
415 .word 0xfffec500
Stefan Roese0df367f2006-05-10 10:55:16 +0200416VAL_MPU_LOAD_TIMER:
417 .word 0xffffffff
418VAL_MPU_CNTL_TIMER:
419 .word 0xffffffa1
wdenk914be132004-06-08 00:22:43 +0000420
421/* 96 MHz Samsung Mobile DDR */
Stefan Roese0df367f2006-05-10 10:55:16 +0200422/* Original setting for TMX device */
423VAL_SDRAM_CONFIG_SDF0:
424 .word 0x0014e6fe
wdenk914be132004-06-08 00:22:43 +0000425
Stefan Roese0df367f2006-05-10 10:55:16 +0200426/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
427VAL_SDRAM_CONFIG_SDF1:
428 .word 0x0114e6fe
wdenk914be132004-06-08 00:22:43 +0000429
430VAL_ARM_CKCTL:
Stefan Roese0df367f2006-05-10 10:55:16 +0200431 .word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */
wdenk914be132004-06-08 00:22:43 +0000432VAL_DPLL1_CTL:
433 .word 0x2830
434
435#ifdef CONFIG_OSK_OMAP5912
436VAL_TC_EMIFS_CS0_CONFIG:
437 .word 0x002130b0
438VAL_TC_EMIFS_CS1_CONFIG:
Stefan Roese9bb01b92006-05-10 11:49:37 +0200439 .word 0x00001133
wdenk914be132004-06-08 00:22:43 +0000440VAL_TC_EMIFS_CS2_CONFIG:
441 .word 0x000055f0
442VAL_TC_EMIFS_CS3_CONFIG:
Stefan Roese0df367f2006-05-10 10:55:16 +0200443 .word 0x88013141
444VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */
445 .word 0x000000c0
446VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */
447 .word 0xb65f
wdenk914be132004-06-08 00:22:43 +0000448#endif
449
450#ifdef CONFIG_H2_OMAP1610
451VAL_TC_EMIFS_CS0_CONFIG:
452 .word 0x00203331
453VAL_TC_EMIFS_CS1_CONFIG:
454 .word 0x8180fff3
455VAL_TC_EMIFS_CS2_CONFIG:
456 .word 0xf800f22a
457VAL_TC_EMIFS_CS3_CONFIG:
Stefan Roese0df367f2006-05-10 10:55:16 +0200458 .word 0x88013141
wdenk914be132004-06-08 00:22:43 +0000459VAL_TC_EMIFS_CS1_ADVANCED:
460 .word 0x00000022
461#endif
462
wdenk914be132004-06-08 00:22:43 +0000463VAL_ARM_IDLECT1:
464 .word 0x00000400
wdenk914be132004-06-08 00:22:43 +0000465VAL_ARM_IDLECT2:
466 .word 0x00000886
467VAL_ARM_IDLECT3:
468 .word 0x00000015
469
Jon Hunterea3814a2013-04-09 16:41:31 -0500470SRAM_STACK:
471 .word CONFIG_SYS_INIT_SP_ADDR
472
wdenk914be132004-06-08 00:22:43 +0000473/* command values */
Stefan Roese0df367f2006-05-10 10:55:16 +0200474.equ CMD_SDRAM_NOP, 0x00000000
475.equ CMD_SDRAM_PRECHARGE, 0x00000001
476.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
477.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007