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git01.mediatek.com / filogic / uboot / 8f7557dee57d903dfdf0f5d677c56b62fa1decd2 / . / board / esd / hub405 / flash.c
blob: 23e81642e02d7951a1a125264b5f0249cd3855c5 [file] [log] [blame]
stroesed558dc42003-09-12 08:41:39 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
stroesed558dc42003-09-12 08:41:39 +0000[diff] [blame]6 */
7
8#include <common.h>
Stefan Roese247e9d72010-09-09 19:18:00 +0200[diff] [blame]9#include <asm/ppc4xx.h>
stroesed558dc42003-09-12 08:41:39 +0000[diff] [blame]10#include <asm/processor.h>
11
12/*
13 * include common flash code (for esd boards)
14 */
15#include "../common/flash.c"
16
17/*-----------------------------------------------------------------------
18 * Functions
19 */
20static ulong flash_get_size (vu_long * addr, flash_info_t * info);
21static void flash_get_offsets (ulong base, flash_info_t * info);
22
23/*-----------------------------------------------------------------------
24 */
25
26unsigned long flash_init (void)
27{
28 unsigned long size_b0;
29 int i;
30 uint pbcr;
31 unsigned long base_b0;
32 int size_val = 0;
33
34 /* Init: no FLASHes known */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]35 for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
stroesed558dc42003-09-12 08:41:39 +0000[diff] [blame]36 flash_info[i].flash_id = FLASH_UNKNOWN;
37 }
38
39 /* Static FLASH Bank configuration here - FIXME XXX */
40
41 size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
42
43 if (flash_info[0].flash_id == FLASH_UNKNOWN) {
44 printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
45 size_b0, size_b0<<20);
46 }
47
48 /* Setup offsets */
49 flash_get_offsets (-size_b0, &flash_info[0]);
50
51 /* Re-do sizing to get full correct info */
Stefan Roese918010a2009-09-09 16:25:29 +0200[diff] [blame]52 mtdcr(EBC0_CFGADDR, PB0CR);
53 pbcr = mfdcr(EBC0_CFGDATA);
54 mtdcr(EBC0_CFGADDR, PB0CR);
stroesed558dc42003-09-12 08:41:39 +0000[diff] [blame]55 base_b0 = -size_b0;
56 switch (size_b0) {
57 case 1 << 20:
58 size_val = 0;
59 break;
60 case 2 << 20:
61 size_val = 1;
62 break;
63 case 4 << 20:
64 size_val = 2;
65 break;
66 case 8 << 20:
67 size_val = 3;
68 break;
69 case 16 << 20:
70 size_val = 4;
71 break;
72 }
73 pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
Stefan Roese918010a2009-09-09 16:25:29 +0200[diff] [blame]74 mtdcr(EBC0_CFGDATA, pbcr);
stroesed558dc42003-09-12 08:41:39 +0000[diff] [blame]75
76 /* Monitor protection ON by default */
77 (void)flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]78 -CONFIG_SYS_MONITOR_LEN,
stroesed558dc42003-09-12 08:41:39 +0000[diff] [blame]79 0xffffffff,
80 &flash_info[0]);
81
82 flash_info[0].size = size_b0;
83
84 return (size_b0);
85}