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git01.mediatek.com / filogic / uboot / 8f440bd40ef2000214cfa8f3eaee7f7fda16d069 / . / include / configs / ethernut5.h
blob: 22647abee0d3f5a74f2d7e1eed27bcaaaa4482a2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]2/*
3 * (C) Copyright 2011
4 * egnite GmbH <info@egnite.de>
5 *
6 * Configuation settings for Ethernut 5 with AT91SAM9XE.
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <asm/hardware.h>
13
14/* The first stage boot loader expects u-boot running at this address. */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]15
16/* The first stage boot loader takes care of low level initialization. */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]17
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]18/* CPU information */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]19
20/* ARM asynchronous clock */
21#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
22#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]23
24/* 32kB internal SRAM */
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]25#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */
26#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]27
28/* 128MB SDRAM in 1 bank */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]29#define CONFIG_SYS_SDRAM_BASE 0x20000000
30#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]31
32/* 512kB on-chip NOR flash */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]33# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]34
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]35
Wenyou.Yang@microchip.comc99bfb42017-07-21 14:30:57 +0800[diff] [blame]36/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]37
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]38/* NAND flash */
39#ifdef CONFIG_CMD_NAND
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]40#define CONFIG_SYS_NAND_BASE 0x40000000
41#define CONFIG_SYS_NAND_DBW_8
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]42/* our ALE is AD21 */
43#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
44/* our CLE is AD22 */
45#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmanna4c24d32013-11-29 12:13:45 +0100[diff] [blame]46#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]47#endif
48
49/* JFFS2 */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]50
51/* Ethernet */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]52#define CONFIG_PHY_ID 0
53#define CONFIG_MACB_SEARCH_PHY
54
55/* MMC */
56#ifdef CONFIG_CMD_MMC
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]57#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
58#endif
59
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]60/* RTC */
61#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]62#define CONFIG_SYS_I2C_RTC_ADDR 0x51
63#endif
64
65/* I2C */
66#define CONFIG_SYS_MAX_I2C_BUS 1
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100[diff] [blame]67
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]68#define I2C_SOFT_DECLARATIONS
69
70#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
71#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
72
73#define I2C_INIT { \
74 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
75 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
76 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
77 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
78 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
79}
80
81#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
82#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
83#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
84#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
85#define I2C_DELAY udelay(100)
86#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
87
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]88/* File systems */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]89
90/* Boot command */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]91
92/* Misc. u-boot settings */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]93
94#endif