blob: 705437862a0d1402f13c4cf0f5e62e6ccabb5d06 [file] [log] [blame]
Lukas Auer83d573d2019-03-17 19:28:32 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Fraunhofer AISEC,
4 * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 */
6
7#include <common.h>
Simon Glass63334482019-11-14 12:57:39 -07008#include <cpu_func.h>
Lukas Auer83d573d2019-03-17 19:28:32 +01009#include <dm.h>
10#include <asm/barrier.h>
11#include <asm/smp.h>
12
13DECLARE_GLOBAL_DATA_PTR;
14
15/**
16 * riscv_send_ipi() - Send inter-processor interrupt (IPI)
17 *
18 * Platform code must provide this function.
19 *
20 * @hart: Hart ID of receiving hart
21 * @return 0 if OK, -ve on error
22 */
23extern int riscv_send_ipi(int hart);
24
25/**
26 * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
27 *
28 * Platform code must provide this function.
29 *
30 * @hart: Hart ID of hart to be cleared
31 * @return 0 if OK, -ve on error
32 */
33extern int riscv_clear_ipi(int hart);
34
35static int send_ipi_many(struct ipi_data *ipi)
36{
37 ofnode node, cpus;
38 u32 reg;
39 int ret;
40
41 cpus = ofnode_path("/cpus");
42 if (!ofnode_valid(cpus)) {
43 pr_err("Can't find cpus node!\n");
44 return -EINVAL;
45 }
46
47 ofnode_for_each_subnode(node, cpus) {
48 /* skip if hart is marked as not available in the device tree */
49 if (!ofnode_is_available(node))
50 continue;
51
52 /* read hart ID of CPU */
53 ret = ofnode_read_u32(node, "reg", &reg);
54 if (ret)
55 continue;
56
57 /* skip if it is the hart we are running on */
58 if (reg == gd->arch.boot_hart)
59 continue;
60
61 if (reg >= CONFIG_NR_CPUS) {
62 pr_err("Hart ID %d is out of range, increase CONFIG_NR_CPUS\n",
63 reg);
64 continue;
65 }
66
Rick Chene5e6c362019-04-30 13:49:33 +080067#ifndef CONFIG_XIP
Lukas Auer83d573d2019-03-17 19:28:32 +010068 /* skip if hart is not available */
69 if (!(gd->arch.available_harts & (1 << reg)))
70 continue;
Rick Chene5e6c362019-04-30 13:49:33 +080071#endif
Lukas Auer83d573d2019-03-17 19:28:32 +010072
73 gd->arch.ipi[reg].addr = ipi->addr;
74 gd->arch.ipi[reg].arg0 = ipi->arg0;
75 gd->arch.ipi[reg].arg1 = ipi->arg1;
76
77 ret = riscv_send_ipi(reg);
78 if (ret) {
79 pr_err("Cannot send IPI to hart %d\n", reg);
80 return ret;
81 }
82 }
83
84 return 0;
85}
86
87void handle_ipi(ulong hart)
88{
89 int ret;
90 void (*smp_function)(ulong hart, ulong arg0, ulong arg1);
91
92 if (hart >= CONFIG_NR_CPUS)
93 return;
94
95 ret = riscv_clear_ipi(hart);
96 if (ret) {
97 pr_err("Cannot clear IPI of hart %ld\n", hart);
98 return;
99 }
100
101 __smp_mb();
102
103 smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
104 invalidate_icache_all();
105
106 smp_function(hart, gd->arch.ipi[hart].arg0, gd->arch.ipi[hart].arg1);
107}
108
109int smp_call_function(ulong addr, ulong arg0, ulong arg1)
110{
111 int ret = 0;
112 struct ipi_data ipi;
113
114 ipi.addr = addr;
115 ipi.arg0 = arg0;
116 ipi.arg1 = arg1;
117
118 ret = send_ipi_many(&ipi);
119
120 return ret;
121}