Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 2 | /* |
Dave Liu | 5245ff5 | 2007-09-18 12:36:11 +0800 | [diff] [blame] | 3 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * CPU specific code for the MPC83xx family. |
| 8 | * |
| 9 | * Derived from the MPC8260 and MPC85xx. |
| 10 | */ |
| 11 | |
| 12 | #include <common.h> |
Simon Glass | 1fa70f8 | 2019-11-14 12:57:34 -0700 | [diff] [blame] | 13 | #include <cpu_func.h> |
Simon Glass | f5c208d | 2019-11-14 12:57:20 -0700 | [diff] [blame] | 14 | #include <vsprintf.h> |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 15 | #include <watchdog.h> |
| 16 | #include <command.h> |
| 17 | #include <mpc83xx.h> |
| 18 | #include <asm/processor.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 19 | #include <linux/libfdt.h> |
Andy Fleming | fecff2b | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 20 | #include <tsec.h> |
Ben Warren | 6773169 | 2008-10-22 23:32:48 -0700 | [diff] [blame] | 21 | #include <netdev.h> |
Andy Fleming | 1463b4b | 2008-10-30 16:50:14 -0500 | [diff] [blame] | 22 | #include <fsl_esdhc.h> |
Mario Six | 9164bdd | 2019-01-21 09:17:25 +0100 | [diff] [blame] | 23 | #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X) |
Zhao Qiang | 978679d | 2014-06-03 16:27:07 +0800 | [diff] [blame] | 24 | #include <linux/immap_qe.h> |
Heiko Schocher | d2c4f3a | 2009-02-24 11:30:51 +0100 | [diff] [blame] | 25 | #include <asm/io.h> |
| 26 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 27 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 28 | DECLARE_GLOBAL_DATA_PTR; |
| 29 | |
Mario Six | 28fbefa | 2018-08-06 10:23:45 +0200 | [diff] [blame] | 30 | #ifndef CONFIG_CPU_MPC83XX |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 31 | int checkcpu(void) |
| 32 | { |
Dave Liu | a46daea | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 33 | volatile immap_t *immr; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 34 | ulong clock = gd->cpu_clk; |
| 35 | u32 pvr = get_pvr(); |
Dave Liu | a46daea | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 36 | u32 spridr; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 37 | char buf[32]; |
Simon Glass | 156283f | 2017-03-28 10:27:27 -0600 | [diff] [blame] | 38 | int ret; |
Kim Phillips | ecb2d6f | 2008-03-28 10:19:07 -0500 | [diff] [blame] | 39 | int i; |
| 40 | |
Kim Phillips | ecb2d6f | 2008-03-28 10:19:07 -0500 | [diff] [blame] | 41 | const struct cpu_type { |
| 42 | char name[15]; |
| 43 | u32 partid; |
| 44 | } cpu_type_list [] = { |
Ilya Yanok | a3e5fd5 | 2010-06-28 16:44:33 +0400 | [diff] [blame] | 45 | CPU_TYPE_ENTRY(8308), |
Gerlando Falauto | fe201cb | 2012-10-10 22:13:08 +0000 | [diff] [blame] | 46 | CPU_TYPE_ENTRY(8309), |
Kim Phillips | ecb2d6f | 2008-03-28 10:19:07 -0500 | [diff] [blame] | 47 | CPU_TYPE_ENTRY(8311), |
| 48 | CPU_TYPE_ENTRY(8313), |
| 49 | CPU_TYPE_ENTRY(8314), |
| 50 | CPU_TYPE_ENTRY(8315), |
| 51 | CPU_TYPE_ENTRY(8321), |
| 52 | CPU_TYPE_ENTRY(8323), |
| 53 | CPU_TYPE_ENTRY(8343), |
| 54 | CPU_TYPE_ENTRY(8347_TBGA_), |
| 55 | CPU_TYPE_ENTRY(8347_PBGA_), |
| 56 | CPU_TYPE_ENTRY(8349), |
| 57 | CPU_TYPE_ENTRY(8358_TBGA_), |
| 58 | CPU_TYPE_ENTRY(8358_PBGA_), |
| 59 | CPU_TYPE_ENTRY(8360), |
| 60 | CPU_TYPE_ENTRY(8377), |
| 61 | CPU_TYPE_ENTRY(8378), |
| 62 | CPU_TYPE_ENTRY(8379), |
| 63 | }; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 64 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 65 | immr = (immap_t *)CONFIG_SYS_IMMR; |
Dave Liu | a46daea | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 66 | |
Simon Glass | 156283f | 2017-03-28 10:27:27 -0600 | [diff] [blame] | 67 | ret = prt_83xx_rsr(); |
| 68 | if (ret) |
| 69 | return ret; |
| 70 | |
Kim Phillips | d82b077 | 2007-04-30 15:26:21 -0500 | [diff] [blame] | 71 | puts("CPU: "); |
Scott Wood | 7206a99 | 2007-04-16 14:34:16 -0500 | [diff] [blame] | 72 | |
| 73 | switch (pvr & 0xffff0000) { |
| 74 | case PVR_E300C1: |
| 75 | printf("e300c1, "); |
| 76 | break; |
| 77 | |
| 78 | case PVR_E300C2: |
| 79 | printf("e300c2, "); |
| 80 | break; |
| 81 | |
| 82 | case PVR_E300C3: |
| 83 | printf("e300c3, "); |
| 84 | break; |
| 85 | |
Dave Liu | 5245ff5 | 2007-09-18 12:36:11 +0800 | [diff] [blame] | 86 | case PVR_E300C4: |
| 87 | printf("e300c4, "); |
| 88 | break; |
| 89 | |
Scott Wood | 7206a99 | 2007-04-16 14:34:16 -0500 | [diff] [blame] | 90 | default: |
| 91 | printf("Unknown core, "); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 92 | } |
| 93 | |
Dave Liu | a46daea | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 94 | spridr = immr->sysconf.spridr; |
Kim Phillips | ecb2d6f | 2008-03-28 10:19:07 -0500 | [diff] [blame] | 95 | |
| 96 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) |
| 97 | if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { |
| 98 | puts("MPC"); |
| 99 | puts(cpu_type_list[i].name); |
| 100 | if (IS_E_PROCESSOR(spridr)) |
| 101 | puts("E"); |
Kim Phillips | 39b4816 | 2010-04-15 17:36:02 -0500 | [diff] [blame] | 102 | if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY || |
| 103 | SPR_FAMILY(spridr) == SPR_836X_FAMILY) && |
| 104 | REVID_MAJOR(spridr) >= 2) |
Kim Phillips | ecb2d6f | 2008-03-28 10:19:07 -0500 | [diff] [blame] | 105 | puts("A"); |
| 106 | printf(", Rev: %d.%d", REVID_MAJOR(spridr), |
| 107 | REVID_MINOR(spridr)); |
| 108 | break; |
| 109 | } |
| 110 | |
| 111 | if (i == ARRAY_SIZE(cpu_type_list)) |
| 112 | printf("(SPRIDR %08x unknown), ", spridr); |
| 113 | |
| 114 | printf(" at %s MHz, ", strmhz(buf, clock)); |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 115 | |
Simon Glass | cc76e9e | 2012-12-13 20:48:47 +0000 | [diff] [blame] | 116 | printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk)); |
Kim Phillips | d82b077 | 2007-04-30 15:26:21 -0500 | [diff] [blame] | 117 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 118 | return 0; |
| 119 | } |
Mario Six | 28fbefa | 2018-08-06 10:23:45 +0200 | [diff] [blame] | 120 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 121 | |
Mario Six | 82ef4ba | 2018-08-06 10:23:35 +0200 | [diff] [blame] | 122 | #ifndef CONFIG_SYSRESET |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 123 | int |
Wolfgang Denk | 6262d021 | 2010-06-28 22:00:46 +0200 | [diff] [blame] | 124 | do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 125 | { |
Wolfgang Denk | 301d096 | 2005-08-05 19:49:35 +0200 | [diff] [blame] | 126 | ulong msr; |
| 127 | #ifndef MPC83xx_RESET |
| 128 | ulong addr; |
| 129 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 130 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 131 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 132 | |
Michael Zaidman | 184154b | 2010-02-15 10:02:32 +0200 | [diff] [blame] | 133 | puts("Resetting the board.\n"); |
| 134 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 135 | #ifdef MPC83xx_RESET |
Michael Zaidman | 184154b | 2010-02-15 10:02:32 +0200 | [diff] [blame] | 136 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 137 | /* Interrupts and MMU off */ |
Mario Six | c463b6d | 2019-01-21 09:18:21 +0100 | [diff] [blame] | 138 | msr = mfmsr(); |
| 139 | msr &= ~(MSR_EE | MSR_IR | MSR_DR); |
| 140 | mtmsr(msr); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 141 | |
| 142 | /* enable Reset Control Reg */ |
| 143 | immap->reset.rpr = 0x52535445; |
Mario Six | c463b6d | 2019-01-21 09:18:21 +0100 | [diff] [blame] | 144 | sync(); |
| 145 | isync(); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 146 | |
| 147 | /* confirm Reset Control Reg is enabled */ |
Mario Six | c463b6d | 2019-01-21 09:18:21 +0100 | [diff] [blame] | 148 | while(!((immap->reset.rcer) & RCER_CRE)) |
| 149 | ; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 150 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 151 | udelay(200); |
| 152 | |
| 153 | /* perform reset, only one bit */ |
Wolfgang Denk | 301d096 | 2005-08-05 19:49:35 +0200 | [diff] [blame] | 154 | immap->reset.rcr = RCR_SWHR; |
| 155 | |
| 156 | #else /* ! MPC83xx_RESET */ |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 157 | |
Wolfgang Denk | 301d096 | 2005-08-05 19:49:35 +0200 | [diff] [blame] | 158 | immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ |
| 159 | |
| 160 | /* Interrupts and MMU off */ |
Mario Six | c463b6d | 2019-01-21 09:18:21 +0100 | [diff] [blame] | 161 | msr = mfmsr(); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 162 | msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); |
Mario Six | c463b6d | 2019-01-21 09:18:21 +0100 | [diff] [blame] | 163 | mtmsr(msr); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 164 | |
| 165 | /* |
| 166 | * Trying to execute the next instruction at a non-existing address |
| 167 | * should cause a machine check, resulting in reset |
| 168 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 169 | addr = CONFIG_SYS_RESET_ADDRESS; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 170 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 171 | ((void (*)(void)) addr) (); |
Wolfgang Denk | 301d096 | 2005-08-05 19:49:35 +0200 | [diff] [blame] | 172 | #endif /* MPC83xx_RESET */ |
| 173 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 174 | return 1; |
| 175 | } |
Mario Six | 82ef4ba | 2018-08-06 10:23:35 +0200 | [diff] [blame] | 176 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 177 | |
| 178 | /* |
| 179 | * Get timebase clock frequency (like cpu_clk in Hz) |
| 180 | */ |
Mario Six | 3c51655 | 2018-08-06 10:23:38 +0200 | [diff] [blame] | 181 | #ifndef CONFIG_TIMER |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 182 | unsigned long get_tbclk(void) |
| 183 | { |
Masahiro Yamada | 04cfea5 | 2016-09-06 22:17:38 +0900 | [diff] [blame] | 184 | return (gd->bus_clk + 3L) / 4L; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 185 | } |
Mario Six | 3c51655 | 2018-08-06 10:23:38 +0200 | [diff] [blame] | 186 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 187 | |
| 188 | #if defined(CONFIG_WATCHDOG) |
| 189 | void watchdog_reset (void) |
| 190 | { |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 191 | int re_enable = disable_interrupts(); |
| 192 | |
| 193 | /* Reset the 83xx watchdog */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 194 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 195 | immr->wdt.swsrr = 0x556c; |
| 196 | immr->wdt.swsrr = 0xaa39; |
| 197 | |
| 198 | if (re_enable) |
Simon Glass | f87959b | 2019-11-14 12:57:40 -0700 | [diff] [blame] | 199 | enable_interrupts(); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 200 | } |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 201 | #endif |
Kumar Gala | 5bbb045 | 2006-01-11 16:48:10 -0600 | [diff] [blame] | 202 | |
Mario Six | 640b8c3 | 2019-01-21 09:18:19 +0100 | [diff] [blame] | 203 | #ifndef CONFIG_DM_ETH |
Andy Fleming | fecff2b | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 204 | /* |
| 205 | * Initializes on-chip ethernet controllers. |
| 206 | * to override, implement board_eth_init() |
Ben Warren | d448a49 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 207 | */ |
Ben Warren | d448a49 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 208 | int cpu_eth_init(bd_t *bis) |
| 209 | { |
Haiying Wang | 511d828 | 2009-06-04 16:12:41 -0400 | [diff] [blame] | 210 | #if defined(CONFIG_UEC_ETH) |
| 211 | uec_standard_init(bis); |
Ben Warren | 6773169 | 2008-10-22 23:32:48 -0700 | [diff] [blame] | 212 | #endif |
Haiying Wang | 511d828 | 2009-06-04 16:12:41 -0400 | [diff] [blame] | 213 | |
Andy Fleming | fecff2b | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 214 | #if defined(CONFIG_TSEC_ENET) |
| 215 | tsec_standard_init(bis); |
Ben Warren | d448a49 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 216 | #endif |
Ben Warren | d448a49 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 217 | return 0; |
| 218 | } |
Mario Six | 640b8c3 | 2019-01-21 09:18:19 +0100 | [diff] [blame] | 219 | #endif /* !CONFIG_DM_ETH */ |
Andy Fleming | 1463b4b | 2008-10-30 16:50:14 -0500 | [diff] [blame] | 220 | |
| 221 | /* |
| 222 | * Initializes on-chip MMC controllers. |
| 223 | * to override, implement board_mmc_init() |
| 224 | */ |
| 225 | int cpu_mmc_init(bd_t *bis) |
| 226 | { |
| 227 | #ifdef CONFIG_FSL_ESDHC |
| 228 | return fsl_esdhc_mmc_init(bis); |
| 229 | #else |
| 230 | return 0; |
| 231 | #endif |
Heiko Schocher | d2c4f3a | 2009-02-24 11:30:51 +0100 | [diff] [blame] | 232 | } |
Mario Six | 90b529f | 2019-01-21 09:18:20 +0100 | [diff] [blame] | 233 | |
| 234 | void ppcDWstore(unsigned int *addr, unsigned int *value) |
| 235 | { |
| 236 | asm("lfd 1, 0(%1)\n\t" |
| 237 | "stfd 1, 0(%0)" |
| 238 | : |
| 239 | : "r" (addr), "r" (value) |
| 240 | : "memory"); |
| 241 | } |
| 242 | |
| 243 | void ppcDWload(unsigned int *addr, unsigned int *ret) |
| 244 | { |
| 245 | asm("lfd 1, 0(%0)\n\t" |
| 246 | "stfd 1, 0(%1)" |
| 247 | : |
| 248 | : "r" (addr), "r" (ret) |
| 249 | : "memory"); |
| 250 | } |