blob: e1d2f2f07cbf3af20d78a1280473db0835c166cb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Eran Liberty9095d4a2005-07-28 10:08:46 -05002/*
Dave Liu5245ff52007-09-18 12:36:11 +08003 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
Eran Liberty9095d4a2005-07-28 10:08:46 -05004 */
5
6/*
7 * CPU specific code for the MPC83xx family.
8 *
9 * Derived from the MPC8260 and MPC85xx.
10 */
11
12#include <common.h>
13#include <watchdog.h>
14#include <command.h>
15#include <mpc83xx.h>
16#include <asm/processor.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090017#include <linux/libfdt.h>
Andy Flemingfecff2b2008-08-31 16:33:26 -050018#include <tsec.h>
Ben Warren67731692008-10-22 23:32:48 -070019#include <netdev.h>
Andy Fleming1463b4b2008-10-30 16:50:14 -050020#include <fsl_esdhc.h>
Heiko Schocher04e3b3a2014-01-25 07:53:47 +010021#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
Zhao Qiang978679d2014-06-03 16:27:07 +080022#include <linux/immap_qe.h>
Heiko Schocherd2c4f3a2009-02-24 11:30:51 +010023#include <asm/io.h>
24#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -050025
Wolfgang Denk6405a152006-03-31 18:32:53 +020026DECLARE_GLOBAL_DATA_PTR;
27
Eran Liberty9095d4a2005-07-28 10:08:46 -050028int checkcpu(void)
29{
Dave Liua46daea2006-11-03 19:33:44 -060030 volatile immap_t *immr;
Eran Liberty9095d4a2005-07-28 10:08:46 -050031 ulong clock = gd->cpu_clk;
32 u32 pvr = get_pvr();
Dave Liua46daea2006-11-03 19:33:44 -060033 u32 spridr;
Eran Liberty9095d4a2005-07-28 10:08:46 -050034 char buf[32];
Simon Glass156283f2017-03-28 10:27:27 -060035 int ret;
Kim Phillipsecb2d6f2008-03-28 10:19:07 -050036 int i;
37
Kim Phillipsecb2d6f2008-03-28 10:19:07 -050038 const struct cpu_type {
39 char name[15];
40 u32 partid;
41 } cpu_type_list [] = {
Ilya Yanoka3e5fd52010-06-28 16:44:33 +040042 CPU_TYPE_ENTRY(8308),
Gerlando Falautofe201cb2012-10-10 22:13:08 +000043 CPU_TYPE_ENTRY(8309),
Kim Phillipsecb2d6f2008-03-28 10:19:07 -050044 CPU_TYPE_ENTRY(8311),
45 CPU_TYPE_ENTRY(8313),
46 CPU_TYPE_ENTRY(8314),
47 CPU_TYPE_ENTRY(8315),
48 CPU_TYPE_ENTRY(8321),
49 CPU_TYPE_ENTRY(8323),
50 CPU_TYPE_ENTRY(8343),
51 CPU_TYPE_ENTRY(8347_TBGA_),
52 CPU_TYPE_ENTRY(8347_PBGA_),
53 CPU_TYPE_ENTRY(8349),
54 CPU_TYPE_ENTRY(8358_TBGA_),
55 CPU_TYPE_ENTRY(8358_PBGA_),
56 CPU_TYPE_ENTRY(8360),
57 CPU_TYPE_ENTRY(8377),
58 CPU_TYPE_ENTRY(8378),
59 CPU_TYPE_ENTRY(8379),
60 };
Eran Liberty9095d4a2005-07-28 10:08:46 -050061
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062 immr = (immap_t *)CONFIG_SYS_IMMR;
Dave Liua46daea2006-11-03 19:33:44 -060063
Simon Glass156283f2017-03-28 10:27:27 -060064 ret = prt_83xx_rsr();
65 if (ret)
66 return ret;
67
Kim Phillipsd82b0772007-04-30 15:26:21 -050068 puts("CPU: ");
Scott Wood7206a992007-04-16 14:34:16 -050069
70 switch (pvr & 0xffff0000) {
71 case PVR_E300C1:
72 printf("e300c1, ");
73 break;
74
75 case PVR_E300C2:
76 printf("e300c2, ");
77 break;
78
79 case PVR_E300C3:
80 printf("e300c3, ");
81 break;
82
Dave Liu5245ff52007-09-18 12:36:11 +080083 case PVR_E300C4:
84 printf("e300c4, ");
85 break;
86
Scott Wood7206a992007-04-16 14:34:16 -050087 default:
88 printf("Unknown core, ");
Eran Liberty9095d4a2005-07-28 10:08:46 -050089 }
90
Dave Liua46daea2006-11-03 19:33:44 -060091 spridr = immr->sysconf.spridr;
Kim Phillipsecb2d6f2008-03-28 10:19:07 -050092
93 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
94 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
95 puts("MPC");
96 puts(cpu_type_list[i].name);
97 if (IS_E_PROCESSOR(spridr))
98 puts("E");
Kim Phillips39b48162010-04-15 17:36:02 -050099 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
100 SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
101 REVID_MAJOR(spridr) >= 2)
Kim Phillipsecb2d6f2008-03-28 10:19:07 -0500102 puts("A");
103 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
104 REVID_MINOR(spridr));
105 break;
106 }
107
108 if (i == ARRAY_SIZE(cpu_type_list))
109 printf("(SPRIDR %08x unknown), ", spridr);
110
111 printf(" at %s MHz, ", strmhz(buf, clock));
Rafal Jaworowski384da5e2005-10-17 02:39:53 +0200112
Simon Glasscc76e9e2012-12-13 20:48:47 +0000113 printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
Kim Phillipsd82b0772007-04-30 15:26:21 -0500114
Eran Liberty9095d4a2005-07-28 10:08:46 -0500115 return 0;
116}
117
Mario Six82ef4ba2018-08-06 10:23:35 +0200118#ifndef CONFIG_SYSRESET
Eran Liberty9095d4a2005-07-28 10:08:46 -0500119int
Wolfgang Denk6262d0212010-06-28 22:00:46 +0200120do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
Eran Liberty9095d4a2005-07-28 10:08:46 -0500121{
Wolfgang Denk301d0962005-08-05 19:49:35 +0200122 ulong msr;
123#ifndef MPC83xx_RESET
124 ulong addr;
125#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500128
Michael Zaidman184154b2010-02-15 10:02:32 +0200129 puts("Resetting the board.\n");
130
Eran Liberty9095d4a2005-07-28 10:08:46 -0500131#ifdef MPC83xx_RESET
Michael Zaidman184154b2010-02-15 10:02:32 +0200132
Eran Liberty9095d4a2005-07-28 10:08:46 -0500133 /* Interrupts and MMU off */
134 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
135
136 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
137 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
138
139 /* enable Reset Control Reg */
140 immap->reset.rpr = 0x52535445;
Marian Balakowicz919b1872006-03-14 16:12:48 +0100141 __asm__ __volatile__ ("sync");
142 __asm__ __volatile__ ("isync");
Eran Liberty9095d4a2005-07-28 10:08:46 -0500143
144 /* confirm Reset Control Reg is enabled */
145 while(!((immap->reset.rcer) & RCER_CRE));
146
Eran Liberty9095d4a2005-07-28 10:08:46 -0500147 udelay(200);
148
149 /* perform reset, only one bit */
Wolfgang Denk301d0962005-08-05 19:49:35 +0200150 immap->reset.rcr = RCR_SWHR;
151
152#else /* ! MPC83xx_RESET */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500153
Wolfgang Denk301d0962005-08-05 19:49:35 +0200154 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
155
156 /* Interrupts and MMU off */
157 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500158
159 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
160 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
161
162 /*
163 * Trying to execute the next instruction at a non-existing address
164 * should cause a machine check, resulting in reset
165 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166 addr = CONFIG_SYS_RESET_ADDRESS;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500167
Eran Liberty9095d4a2005-07-28 10:08:46 -0500168 ((void (*)(void)) addr) ();
Wolfgang Denk301d0962005-08-05 19:49:35 +0200169#endif /* MPC83xx_RESET */
170
Eran Liberty9095d4a2005-07-28 10:08:46 -0500171 return 1;
172}
Mario Six82ef4ba2018-08-06 10:23:35 +0200173#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500174
175/*
176 * Get timebase clock frequency (like cpu_clk in Hz)
177 */
178
179unsigned long get_tbclk(void)
180{
Masahiro Yamada04cfea52016-09-06 22:17:38 +0900181 return (gd->bus_clk + 3L) / 4L;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500182}
183
184
185#if defined(CONFIG_WATCHDOG)
186void watchdog_reset (void)
187{
Timur Tabi054838e2006-10-31 18:44:42 -0600188 int re_enable = disable_interrupts();
189
190 /* Reset the 83xx watchdog */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
Timur Tabi054838e2006-10-31 18:44:42 -0600192 immr->wdt.swsrr = 0x556c;
193 immr->wdt.swsrr = 0xaa39;
194
195 if (re_enable)
196 enable_interrupts ();
Eran Liberty9095d4a2005-07-28 10:08:46 -0500197}
Timur Tabi054838e2006-10-31 18:44:42 -0600198#endif
Kumar Gala5bbb0452006-01-11 16:48:10 -0600199
Andy Flemingfecff2b2008-08-31 16:33:26 -0500200/*
201 * Initializes on-chip ethernet controllers.
202 * to override, implement board_eth_init()
Ben Warrend448a492008-06-23 22:57:27 -0700203 */
Ben Warrend448a492008-06-23 22:57:27 -0700204int cpu_eth_init(bd_t *bis)
205{
Haiying Wang511d8282009-06-04 16:12:41 -0400206#if defined(CONFIG_UEC_ETH)
207 uec_standard_init(bis);
Ben Warren67731692008-10-22 23:32:48 -0700208#endif
Haiying Wang511d8282009-06-04 16:12:41 -0400209
Andy Flemingfecff2b2008-08-31 16:33:26 -0500210#if defined(CONFIG_TSEC_ENET)
211 tsec_standard_init(bis);
Ben Warrend448a492008-06-23 22:57:27 -0700212#endif
Ben Warrend448a492008-06-23 22:57:27 -0700213 return 0;
214}
Andy Fleming1463b4b2008-10-30 16:50:14 -0500215
216/*
217 * Initializes on-chip MMC controllers.
218 * to override, implement board_mmc_init()
219 */
220int cpu_mmc_init(bd_t *bis)
221{
222#ifdef CONFIG_FSL_ESDHC
223 return fsl_esdhc_mmc_init(bis);
224#else
225 return 0;
226#endif
Heiko Schocherd2c4f3a2009-02-24 11:30:51 +0100227}