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git01.mediatek.com / filogic / uboot / 8f37ac40f7db756a5d8eb3a4418bed0186925619 / . / include / configs / smdkv310.h
blob: f113fa44045e94ccc3204369b278c56a6de2ff77 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]2/*
3 * Copyright (C) 2011 Samsung Electronics
4 *
Chander Kashyap4131a772011-12-06 23:34:12 +0000[diff] [blame]5 * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Simon Glass05b3bac32014-10-07 22:01:49 -0600[diff] [blame]11#include "exynos4-common.h"
12
13#undef CONFIG_BOARD_COMMON
Marek Vasutbc623f22015-08-19 23:27:26 +0200[diff] [blame]14#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
Simon Glass05b3bac32014-10-07 22:01:49 -0600[diff] [blame]15
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]16/* High Level Configuration Options */
Chander Kashyap4131a772011-12-06 23:34:12 +0000[diff] [blame]17#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]18
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]19#define CONFIG_SYS_SDRAM_BASE 0x40000000
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]20
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]21/* Handling Sleep Mode*/
22#define S5P_CHECK_SLEEP 0x00000BAD
23#define S5P_CHECK_DIDLE 0xBAD00000
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530[diff] [blame]24#define S5P_CHECK_LPA 0xABAD0000
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]25
Chander Kashyap0cd984c2011-09-20 21:25:03 +0000[diff] [blame]26/* MMC SPL */
Chander Kashyape8d043e2011-09-20 21:25:04 +0000[diff] [blame]27#define COPY_BL2_FNPTR_ADDR 0x00002488
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]28
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]29/* SMDKV310 has 4 bank of DRAM */
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]30#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
31#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
32#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
33#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
34#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
35#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
36#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
37#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
38#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
39
40/* FLASH and environment organization */
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]41
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]42#define CONFIG_CLK_1000_400_200
43
44/* MIU (Memory Interleaving Unit) */
45#define CONFIG_MIU_2BIT_INTERLEAVED
46
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]47#define RESERVE_BLOCK_SIZE (512)
48#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]49
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530[diff] [blame]50#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
51
52#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]53
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame]54/* U-Boot copy size from boot Media to DRAM.*/
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]55#define COPY_BL2_SIZE 0x80000
56#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
57#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
58
59/* Ethernet Controllor Driver */
60#ifdef CONFIG_CMD_NET
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]61#define CONFIG_ENV_SROM_BANK 1
62#endif /*CONFIG_CMD_NET*/
Thomas Abraham4cd38a42011-06-03 22:52:17 +0000[diff] [blame]63
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]64#endif /* __CONFIG_H */