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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sascha Hauer15ea70f2008-03-26 20:40:49 +01002/*
Marek Vasut94cb8422011-09-22 09:22:12 +00003 * i2c driver for Freescale i.MX series
Sascha Hauer15ea70f2008-03-26 20:40:49 +01004 *
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
Marek Vasut94cb8422011-09-22 09:22:12 +00006 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 *
8 * Based on i2c-imx.c from linux kernel:
9 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
10 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
11 * Copyright (C) 2007 RightHand Technologies, Inc.
12 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
13 *
Sascha Hauer15ea70f2008-03-26 20:40:49 +010014 */
15
16#include <common.h>
Liu Hui-R64343447beb12011-01-03 22:27:39 +000017#include <asm/arch/clock.h>
Stefano Babic78129d92011-03-14 15:43:56 +010018#include <asm/arch/imx-regs.h>
Simon Glass9bc15642020-02-03 07:36:16 -070019#include <dm/device_compat.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090020#include <linux/errno.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020021#include <asm/mach-imx/mxc_i2c.h>
Peng Fan23d4ee32020-05-01 22:08:35 +080022#include <asm/mach-imx/sys_proto.h>
Troy Kisky2254b7f2012-07-19 08:18:03 +000023#include <asm/io.h>
Marek Vasut5f1291e2011-10-26 00:05:44 +000024#include <i2c.h>
Troy Kiskyf024a3b2012-07-19 08:18:09 +000025#include <watchdog.h>
Peng Fan8262cb12015-05-15 07:29:12 +080026#include <dm.h>
Peng Fan4f1a5812016-03-11 16:47:50 +080027#include <dm/pinctrl.h>
Peng Fan8262cb12015-05-15 07:29:12 +080028#include <fdtdec.h>
Sascha Hauer15ea70f2008-03-26 20:40:49 +010029
York Suna4c02662014-02-10 14:02:52 -080030DECLARE_GLOBAL_DATA_PTR;
31
Peng Fan8262cb12015-05-15 07:29:12 +080032#define I2C_QUIRK_FLAG (1 << 0)
33
34#define IMX_I2C_REGSHIFT 2
35#define VF610_I2C_REGSHIFT 0
Yuan Yaod40c8852016-06-08 18:24:51 +080036
37#define I2C_EARLY_INIT_INDEX 0
38#ifdef CONFIG_SYS_I2C_IFDR_DIV
39#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
40#else
41#define I2C_IFDR_DIV_CONSERVATIVE 0x7e
42#endif
43
Peng Fan8262cb12015-05-15 07:29:12 +080044/* Register index */
45#define IADR 0
46#define IFDR 1
47#define I2CR 2
48#define I2SR 3
49#define I2DR 4
Sascha Hauer15ea70f2008-03-26 20:40:49 +010050
Sascha Hauer15ea70f2008-03-26 20:40:49 +010051#define I2CR_IIEN (1 << 6)
52#define I2CR_MSTA (1 << 5)
53#define I2CR_MTX (1 << 4)
54#define I2CR_TX_NO_AK (1 << 3)
55#define I2CR_RSTA (1 << 2)
56
57#define I2SR_ICF (1 << 7)
58#define I2SR_IBB (1 << 5)
Troy Kisky8ff683a2012-07-19 08:18:15 +000059#define I2SR_IAL (1 << 4)
Sascha Hauer15ea70f2008-03-26 20:40:49 +010060#define I2SR_IIF (1 << 1)
61#define I2SR_RX_NO_AK (1 << 0)
62
Alison Wangcf508002013-06-17 15:30:39 +080063#ifdef I2C_QUIRK_REG
64#define I2CR_IEN (0 << 7)
65#define I2CR_IDIS (1 << 7)
66#define I2SR_IIF_CLEAR (1 << 1)
67#else
68#define I2CR_IEN (1 << 7)
69#define I2CR_IDIS (0 << 7)
70#define I2SR_IIF_CLEAR (0 << 1)
71#endif
72
Alison Wangcf508002013-06-17 15:30:39 +080073#ifdef I2C_QUIRK_REG
74static u16 i2c_clk_div[60][2] = {
75 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
76 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
77 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
78 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
79 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
80 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
81 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
82 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
83 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
84 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
85 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
86 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
87 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
88 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
89 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
90};
91#else
Marek Vasut94cb8422011-09-22 09:22:12 +000092static u16 i2c_clk_div[50][2] = {
93 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
94 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
95 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
96 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
97 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
98 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
99 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
100 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
101 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
102 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
103 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
104 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
105 { 3072, 0x1E }, { 3840, 0x1F }
106};
Alison Wangcf508002013-06-17 15:30:39 +0800107#endif
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100108
trema49f40a2013-09-21 18:13:35 +0200109#ifndef CONFIG_SYS_MXC_I2C1_SPEED
110#define CONFIG_SYS_MXC_I2C1_SPEED 100000
111#endif
112#ifndef CONFIG_SYS_MXC_I2C2_SPEED
113#define CONFIG_SYS_MXC_I2C2_SPEED 100000
114#endif
115#ifndef CONFIG_SYS_MXC_I2C3_SPEED
116#define CONFIG_SYS_MXC_I2C3_SPEED 100000
117#endif
York Sunf1a52162015-03-20 10:20:40 -0700118#ifndef CONFIG_SYS_MXC_I2C4_SPEED
119#define CONFIG_SYS_MXC_I2C4_SPEED 100000
120#endif
trema49f40a2013-09-21 18:13:35 +0200121
122#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
123#define CONFIG_SYS_MXC_I2C1_SLAVE 0
124#endif
125#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
126#define CONFIG_SYS_MXC_I2C2_SLAVE 0
127#endif
128#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
129#define CONFIG_SYS_MXC_I2C3_SLAVE 0
130#endif
York Sunf1a52162015-03-20 10:20:40 -0700131#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
132#define CONFIG_SYS_MXC_I2C4_SLAVE 0
133#endif
trema49f40a2013-09-21 18:13:35 +0200134
Marek Vasut94cb8422011-09-22 09:22:12 +0000135/*
136 * Calculate and set proper clock divider
137 */
Peng Fan8262cb12015-05-15 07:29:12 +0800138static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100139{
Marek Vasut94cb8422011-09-22 09:22:12 +0000140 unsigned int i2c_clk_rate;
141 unsigned int div;
Marek Vasut5f1291e2011-10-26 00:05:44 +0000142 u8 clk_div;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100143
Liu Hui-R64343447beb12011-01-03 22:27:39 +0000144#if defined(CONFIG_MX31)
Stefano Babic22121722011-01-20 07:50:44 +0000145 struct clock_control_regs *sc_regs =
146 (struct clock_control_regs *)CCM_BASE;
Marek Vasut94cb8422011-09-22 09:22:12 +0000147
Guennadi Liakhovetski3314fc62009-02-13 09:23:36 +0100148 /* start the required I2C clock */
Troy Kisky8462c632012-04-24 17:33:25 +0000149 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
Stefano Babic22121722011-01-20 07:50:44 +0000150 &sc_regs->cgr0);
Liu Hui-R64343447beb12011-01-03 22:27:39 +0000151#endif
Guennadi Liakhovetski3314fc62009-02-13 09:23:36 +0100152
Marek Vasut94cb8422011-09-22 09:22:12 +0000153 /* Divider value calculation */
Peng Fan87ea5622019-08-08 01:43:30 +0000154#if CONFIG_IS_ENABLED(CLK)
155 i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
156#else
Matthias Weisser99ba3422012-09-24 02:46:53 +0000157 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
Peng Fan87ea5622019-08-08 01:43:30 +0000158#endif
159
Marek Vasut94cb8422011-09-22 09:22:12 +0000160 div = (i2c_clk_rate + rate - 1) / rate;
161 if (div < i2c_clk_div[0][0])
Marek Vasut4f274442011-09-27 06:34:11 +0000162 clk_div = 0;
Marek Vasut94cb8422011-09-22 09:22:12 +0000163 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
Marek Vasut4f274442011-09-27 06:34:11 +0000164 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
Marek Vasut94cb8422011-09-22 09:22:12 +0000165 else
Marek Vasut4f274442011-09-27 06:34:11 +0000166 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
Marek Vasut94cb8422011-09-22 09:22:12 +0000167 ;
168
169 /* Store divider value */
Marek Vasut5f1291e2011-10-26 00:05:44 +0000170 return clk_div;
Marek Vasut94cb8422011-09-22 09:22:12 +0000171}
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100172
Marek Vasut94cb8422011-09-22 09:22:12 +0000173/*
Troy Kiskyae447602012-07-19 08:18:18 +0000174 * Set I2C Bus speed
Marek Vasut94cb8422011-09-22 09:22:12 +0000175 */
Peng Fan8262cb12015-05-15 07:29:12 +0800176static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
Marek Vasut94cb8422011-09-22 09:22:12 +0000177{
Peng Fan8262cb12015-05-15 07:29:12 +0800178 ulong base = i2c_bus->base;
179 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
180 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
Marek Vasut5f1291e2011-10-26 00:05:44 +0000181 u8 idx = i2c_clk_div[clk_idx][1];
Peng Fan8262cb12015-05-15 07:29:12 +0800182 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Marek Vasut5f1291e2011-10-26 00:05:44 +0000183
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200184 if (!base)
Simon Glassf44b4bf2017-09-17 16:54:53 -0600185 return -EINVAL;
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200186
Marek Vasut5f1291e2011-10-26 00:05:44 +0000187 /* Store divider value */
Peng Fan8262cb12015-05-15 07:29:12 +0800188 writeb(idx, base + (IFDR << reg_shift));
Marek Vasut5f1291e2011-10-26 00:05:44 +0000189
Troy Kiskye6fa4d72012-07-19 08:18:12 +0000190 /* Reset module */
Peng Fan8262cb12015-05-15 07:29:12 +0800191 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
192 writeb(0, base + (I2SR << reg_shift));
Marek Vasut4f274442011-09-27 06:34:11 +0000193 return 0;
194}
195
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000196#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
197#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
198#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
Stefano Babic848bb992011-01-20 07:51:31 +0000199
Peng Fan8262cb12015-05-15 07:29:12 +0800200static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100201{
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000202 unsigned sr;
203 ulong elapsed;
Peng Fan8262cb12015-05-15 07:29:12 +0800204 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
205 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
206 ulong base = i2c_bus->base;
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000207 ulong start_time = get_timer(0);
208 for (;;) {
Peng Fan8262cb12015-05-15 07:29:12 +0800209 sr = readb(base + (I2SR << reg_shift));
Troy Kisky8ff683a2012-07-19 08:18:15 +0000210 if (sr & I2SR_IAL) {
Peng Fan8262cb12015-05-15 07:29:12 +0800211 if (quirk)
212 writeb(sr | I2SR_IAL, base +
213 (I2SR << reg_shift));
214 else
215 writeb(sr & ~I2SR_IAL, base +
216 (I2SR << reg_shift));
Troy Kisky8ff683a2012-07-19 08:18:15 +0000217 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
Peng Fan8262cb12015-05-15 07:29:12 +0800218 __func__, sr, readb(base + (I2CR << reg_shift)),
219 state);
Troy Kisky8ff683a2012-07-19 08:18:15 +0000220 return -ERESTART;
221 }
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000222 if ((sr & (state >> 8)) == (unsigned char)state)
223 return sr;
224 WATCHDOG_RESET();
225 elapsed = get_timer(start_time);
226 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
227 break;
Marek Vasut94cb8422011-09-22 09:22:12 +0000228 }
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000229 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
Peng Fan8262cb12015-05-15 07:29:12 +0800230 sr, readb(base + (I2CR << reg_shift)), state);
Troy Kisky752ac8f2012-07-19 08:18:04 +0000231 return -ETIMEDOUT;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100232}
233
Peng Fan8262cb12015-05-15 07:29:12 +0800234static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
Stefano Babic848bb992011-01-20 07:51:31 +0000235{
Troy Kisky752ac8f2012-07-19 08:18:04 +0000236 int ret;
Peng Fan8262cb12015-05-15 07:29:12 +0800237 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
238 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
239 ulong base = i2c_bus->base;
Stefano Babic848bb992011-01-20 07:51:31 +0000240
Peng Fan8262cb12015-05-15 07:29:12 +0800241 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
242 writeb(byte, base + (I2DR << reg_shift));
243
244 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kisky752ac8f2012-07-19 08:18:04 +0000245 if (ret < 0)
246 return ret;
Troy Kisky752ac8f2012-07-19 08:18:04 +0000247 if (ret & I2SR_RX_NO_AK)
Simon Glassf44b4bf2017-09-17 16:54:53 -0600248 return -EREMOTEIO;
Troy Kisky752ac8f2012-07-19 08:18:04 +0000249 return 0;
Marek Vasut94cb8422011-09-22 09:22:12 +0000250}
Peng Fan8262cb12015-05-15 07:29:12 +0800251
252/*
253 * Stub implementations for outer i2c slave operations.
254 */
255void __i2c_force_reset_slave(void)
256{
257}
258void i2c_force_reset_slave(void)
259 __attribute__((weak, alias("__i2c_force_reset_slave")));
Stefano Babic848bb992011-01-20 07:51:31 +0000260
Marek Vasut94cb8422011-09-22 09:22:12 +0000261/*
Troy Kiskyfef163f2012-07-19 08:18:13 +0000262 * Stop I2C transaction
Marek Vasut94cb8422011-09-22 09:22:12 +0000263 */
Peng Fan8262cb12015-05-15 07:29:12 +0800264static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100265{
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000266 int ret;
Peng Fan8262cb12015-05-15 07:29:12 +0800267 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
268 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
269 ulong base = i2c_bus->base;
270 unsigned int temp = readb(base + (I2CR << reg_shift));
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100271
Troy Kisky1ac1e452012-07-19 08:18:02 +0000272 temp &= ~(I2CR_MSTA | I2CR_MTX);
Peng Fan8262cb12015-05-15 07:29:12 +0800273 writeb(temp, base + (I2CR << reg_shift));
274 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000275 if (ret < 0)
276 printf("%s:trigger stop failed\n", __func__);
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100277}
278
Marek Vasut94cb8422011-09-22 09:22:12 +0000279/*
Troy Kisky14db6f22012-07-19 08:18:06 +0000280 * Send start signal, chip address and
281 * write register address
Marek Vasut94cb8422011-09-22 09:22:12 +0000282 */
Peng Fan8262cb12015-05-15 07:29:12 +0800283static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
284 u32 addr, int alen)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100285{
Troy Kiskya974bcc2012-07-19 08:18:11 +0000286 unsigned int temp;
287 int ret;
Peng Fan8262cb12015-05-15 07:29:12 +0800288 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
289 ulong base = i2c_bus->base;
290 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
291
292 /* Reset i2c slave */
293 i2c_force_reset_slave();
Troy Kiskya974bcc2012-07-19 08:18:11 +0000294
295 /* Enable I2C controller */
Peng Fan8262cb12015-05-15 07:29:12 +0800296 if (quirk)
297 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
298 else
299 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
300
301 if (ret) {
302 writeb(I2CR_IEN, base + (I2CR << reg_shift));
Troy Kiskyfef163f2012-07-19 08:18:13 +0000303 /* Wait for controller to be stable */
304 udelay(50);
305 }
Peng Fan8262cb12015-05-15 07:29:12 +0800306
307 if (readb(base + (IADR << reg_shift)) == (chip << 1))
308 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
309 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
310 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kiskyfef163f2012-07-19 08:18:13 +0000311 if (ret < 0)
Troy Kiskyeca037a2012-07-19 08:18:16 +0000312 return ret;
Troy Kiskya974bcc2012-07-19 08:18:11 +0000313
314 /* Start I2C transaction */
Peng Fan8262cb12015-05-15 07:29:12 +0800315 temp = readb(base + (I2CR << reg_shift));
Troy Kiskya974bcc2012-07-19 08:18:11 +0000316 temp |= I2CR_MSTA;
Peng Fan8262cb12015-05-15 07:29:12 +0800317 writeb(temp, base + (I2CR << reg_shift));
Troy Kiskya974bcc2012-07-19 08:18:11 +0000318
Peng Fan8262cb12015-05-15 07:29:12 +0800319 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
Troy Kiskya974bcc2012-07-19 08:18:11 +0000320 if (ret < 0)
Troy Kiskyeca037a2012-07-19 08:18:16 +0000321 return ret;
Troy Kisky14db6f22012-07-19 08:18:06 +0000322
Troy Kiskya974bcc2012-07-19 08:18:11 +0000323 temp |= I2CR_MTX | I2CR_TX_NO_AK;
Peng Fan8262cb12015-05-15 07:29:12 +0800324 writeb(temp, base + (I2CR << reg_shift));
Troy Kiskya974bcc2012-07-19 08:18:11 +0000325
Nandor Hana51f9da2017-11-08 15:35:09 +0000326 if (alen >= 0) {
327 /* write slave address */
328 ret = tx_byte(i2c_bus, chip << 1);
Troy Kisky752ac8f2012-07-19 08:18:04 +0000329 if (ret < 0)
Troy Kiskyeca037a2012-07-19 08:18:16 +0000330 return ret;
Nandor Hana51f9da2017-11-08 15:35:09 +0000331
332 while (alen--) {
333 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
334 if (ret < 0)
335 return ret;
336 }
Stefano Babic848bb992011-01-20 07:51:31 +0000337 }
Nandor Hana51f9da2017-11-08 15:35:09 +0000338
Troy Kisky14db6f22012-07-19 08:18:06 +0000339 return 0;
Troy Kiskyeca037a2012-07-19 08:18:16 +0000340}
341
Peng Fan8262cb12015-05-15 07:29:12 +0800342#ifndef CONFIG_DM_I2C
343int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
344{
345 if (i2c_bus && i2c_bus->idle_bus_fn)
346 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
347 return 0;
348}
349#else
350/*
Peng Fan4f1a5812016-03-11 16:47:50 +0800351 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
352 * "
353 * scl-gpios: specify the gpio related to SCL pin
354 * sda-gpios: specify the gpio related to SDA pin
355 * add pinctrl to configure i2c pins to gpio function for i2c
356 * bus recovery, call it "gpio" state
357 * "
358 *
359 * The i2c_idle_bus is an implementation following Linux Kernel.
Peng Fan8262cb12015-05-15 07:29:12 +0800360 */
Peng Fan4f1a5812016-03-11 16:47:50 +0800361int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
Peng Fan8262cb12015-05-15 07:29:12 +0800362{
Peng Fan4f1a5812016-03-11 16:47:50 +0800363 struct udevice *bus = i2c_bus->bus;
Lukasz Majewskibc9aad62019-04-04 12:35:34 +0200364 struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
Peng Fan4f1a5812016-03-11 16:47:50 +0800365 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
366 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
Lukasz Majewskibc9aad62019-04-04 12:35:34 +0200367 int sda, scl, idle_sclks;
Peng Fan4f1a5812016-03-11 16:47:50 +0800368 int i, ret = 0;
369 ulong elapsed, start_time;
Peng Fan8262cb12015-05-15 07:29:12 +0800370
Peng Fan4f1a5812016-03-11 16:47:50 +0800371 if (pinctrl_select_state(bus, "gpio")) {
372 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
373 /*
374 * GPIO pinctrl for i2c force idle is not a must,
375 * but it is strongly recommended to be used.
376 * Because it can help you to recover from bad
377 * i2c bus state. Do not return failure, because
378 * it is not a must.
379 */
380 return 0;
381 }
382
383 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
384 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
385 scl = dm_gpio_get_value(scl_gpio);
386 sda = dm_gpio_get_value(sda_gpio);
387
388 if ((sda & scl) == 1)
389 goto exit; /* Bus is idle already */
390
Lukasz Majewskibc9aad62019-04-04 12:35:34 +0200391 /*
392 * In most cases it is just enough to generate 8 + 1 SCLK
393 * clocks to recover I2C slave device from 'stuck' state
394 * (when for example SW reset was performed, in the middle of
395 * I2C transmission).
396 *
397 * However, there are devices which send data in packets of
398 * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
399 * clocks.
400 */
401 idle_sclks = 8 + 1;
402
403 if (i2c->max_transaction_bytes > 0)
404 idle_sclks = i2c->max_transaction_bytes * 8 + 1;
Peng Fan4f1a5812016-03-11 16:47:50 +0800405 /* Send high and low on the SCL line */
Lukasz Majewskibc9aad62019-04-04 12:35:34 +0200406 for (i = 0; i < idle_sclks; i++) {
Peng Fan4f1a5812016-03-11 16:47:50 +0800407 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
408 dm_gpio_set_value(scl_gpio, 0);
409 udelay(50);
410 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
411 udelay(50);
412 }
413 start_time = get_timer(0);
414 for (;;) {
415 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
416 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
417 scl = dm_gpio_get_value(scl_gpio);
418 sda = dm_gpio_get_value(sda_gpio);
419 if ((sda & scl) == 1)
420 break;
421 WATCHDOG_RESET();
422 elapsed = get_timer(start_time);
423 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
424 ret = -EBUSY;
425 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
426 break;
427 }
428 }
429
430exit:
431 pinctrl_select_state(bus, "default");
432 return ret;
433}
Peng Fan8262cb12015-05-15 07:29:12 +0800434#endif
Troy Kiskya23ab222012-07-19 08:18:19 +0000435
Peng Fan8262cb12015-05-15 07:29:12 +0800436static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
437 u32 addr, int alen)
Troy Kiskyeca037a2012-07-19 08:18:16 +0000438{
439 int retry;
440 int ret;
Peng Fan8262cb12015-05-15 07:29:12 +0800441 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
442 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200443
444 if (!i2c_bus->base)
Simon Glassf44b4bf2017-09-17 16:54:53 -0600445 return -EINVAL;
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200446
Troy Kiskyeca037a2012-07-19 08:18:16 +0000447 for (retry = 0; retry < 3; retry++) {
Peng Fan8262cb12015-05-15 07:29:12 +0800448 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
Troy Kiskyeca037a2012-07-19 08:18:16 +0000449 if (ret >= 0)
450 return 0;
Peng Fan8262cb12015-05-15 07:29:12 +0800451 i2c_imx_stop(i2c_bus);
Simon Glassf44b4bf2017-09-17 16:54:53 -0600452 if (ret == -EREMOTEIO)
Troy Kiskyeca037a2012-07-19 08:18:16 +0000453 return ret;
454
455 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
456 retry);
457 if (ret != -ERESTART)
Alison Wangcf508002013-06-17 15:30:39 +0800458 /* Disable controller */
Peng Fan8262cb12015-05-15 07:29:12 +0800459 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
Troy Kiskyeca037a2012-07-19 08:18:16 +0000460 udelay(100);
Peng Fan8262cb12015-05-15 07:29:12 +0800461 if (i2c_idle_bus(i2c_bus) < 0)
Troy Kiskya23ab222012-07-19 08:18:19 +0000462 break;
Troy Kiskyeca037a2012-07-19 08:18:16 +0000463 }
Peng Fan8262cb12015-05-15 07:29:12 +0800464 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
Marek Vasut94cb8422011-09-22 09:22:12 +0000465 return ret;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100466}
467
Peng Fan8262cb12015-05-15 07:29:12 +0800468
469static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
470 int len)
471{
472 int i, ret = 0;
473
474 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
475 debug("write_data: ");
476 /* use rc for counter */
477 for (i = 0; i < len; ++i)
478 debug(" 0x%02x", buf[i]);
479 debug("\n");
480
481 for (i = 0; i < len; i++) {
482 ret = tx_byte(i2c_bus, buf[i]);
483 if (ret < 0) {
484 debug("i2c_write_data(): rc=%d\n", ret);
485 break;
486 }
487 }
488
489 return ret;
490}
491
Trent Piepho9c896a92019-04-30 16:08:19 +0000492/* Will generate a STOP after the last byte if "last" is true, i.e. this is the
493 * final message of a transaction. If not, it switches the bus back to TX mode
494 * and does not send a STOP, leaving the bus in a state where a repeated start
495 * and address can be sent for another message.
496 */
Peng Fan8262cb12015-05-15 07:29:12 +0800497static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
Trent Piepho9c896a92019-04-30 16:08:19 +0000498 int len, bool last)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100499{
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100500 int ret;
Marek Vasut94cb8422011-09-22 09:22:12 +0000501 unsigned int temp;
502 int i;
Peng Fan8262cb12015-05-15 07:29:12 +0800503 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
504 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
505 ulong base = i2c_bus->base;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100506
Peng Fan8262cb12015-05-15 07:29:12 +0800507 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100508
Marek Vasut94cb8422011-09-22 09:22:12 +0000509 /* setup bus to read data */
Peng Fan8262cb12015-05-15 07:29:12 +0800510 temp = readb(base + (I2CR << reg_shift));
Marek Vasut94cb8422011-09-22 09:22:12 +0000511 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
512 if (len == 1)
513 temp |= I2CR_TX_NO_AK;
Peng Fan8262cb12015-05-15 07:29:12 +0800514 writeb(temp, base + (I2CR << reg_shift));
515 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
516 /* dummy read to clear ICF */
517 readb(base + (I2DR << reg_shift));
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100518
Marek Vasut94cb8422011-09-22 09:22:12 +0000519 /* read data */
520 for (i = 0; i < len; i++) {
Peng Fan8262cb12015-05-15 07:29:12 +0800521 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000522 if (ret < 0) {
Peng Fan8262cb12015-05-15 07:29:12 +0800523 debug("i2c_read_data(): ret=%d\n", ret);
524 i2c_imx_stop(i2c_bus);
Marek Vasut94cb8422011-09-22 09:22:12 +0000525 return ret;
Troy Kisky0ce898d2012-07-19 08:18:07 +0000526 }
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100527
Marek Vasut94cb8422011-09-22 09:22:12 +0000528 if (i == (len - 1)) {
Trent Piepho9c896a92019-04-30 16:08:19 +0000529 /* Final byte has already been received by master! When
530 * we read it from I2DR, the master will start another
531 * cycle. We must program it first to send a STOP or
532 * switch to TX to avoid this.
533 */
534 if (last) {
535 i2c_imx_stop(i2c_bus);
536 } else {
537 /* Final read, no stop, switch back to tx */
538 temp = readb(base + (I2CR << reg_shift));
539 temp |= I2CR_MTX | I2CR_TX_NO_AK;
540 writeb(temp, base + (I2CR << reg_shift));
541 }
Marek Vasut94cb8422011-09-22 09:22:12 +0000542 } else if (i == (len - 2)) {
Trent Piepho9c896a92019-04-30 16:08:19 +0000543 /* Master has already recevied penultimate byte. When
544 * we read it from I2DR, master will start RX of final
545 * byte. We must set TX_NO_AK now so it does not ACK
546 * that final byte.
547 */
Peng Fan8262cb12015-05-15 07:29:12 +0800548 temp = readb(base + (I2CR << reg_shift));
Marek Vasut94cb8422011-09-22 09:22:12 +0000549 temp |= I2CR_TX_NO_AK;
Peng Fan8262cb12015-05-15 07:29:12 +0800550 writeb(temp, base + (I2CR << reg_shift));
Marek Vasut94cb8422011-09-22 09:22:12 +0000551 }
Trent Piepho9c896a92019-04-30 16:08:19 +0000552
Peng Fan8262cb12015-05-15 07:29:12 +0800553 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
554 buf[i] = readb(base + (I2DR << reg_shift));
Marek Vasut94cb8422011-09-22 09:22:12 +0000555 }
Peng Fan8262cb12015-05-15 07:29:12 +0800556
557 /* reuse ret for counter*/
558 for (ret = 0; ret < len; ++ret)
559 debug(" 0x%02x", buf[ret]);
560 debug("\n");
561
Trent Piepho9c896a92019-04-30 16:08:19 +0000562 /* It is not clear to me that this is necessary */
563 if (last)
564 i2c_imx_stop(i2c_bus);
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000565 return 0;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100566}
567
Chuanhua Hand24d2d92019-07-10 21:00:22 +0800568int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
569{
570 return 1;
571}
572
573int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
574 __attribute__((weak, alias("__enable_i2c_clk")));
575
Peng Fan8262cb12015-05-15 07:29:12 +0800576#ifndef CONFIG_DM_I2C
Marek Vasut94cb8422011-09-22 09:22:12 +0000577/*
Peng Fan8262cb12015-05-15 07:29:12 +0800578 * Read data from I2C device
Trent Piepho15410ba2019-04-30 16:08:18 +0000579 *
580 * The transactions use the syntax defined in the Linux kernel I2C docs.
581 *
582 * If alen is > 0, then this function will send a transaction of the form:
583 * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
584 * This is a normal I2C register read: writing the register address, then doing
585 * a repeated start and reading the data.
586 *
587 * If alen == 0, then we get this transaction:
588 * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
589 * This is somewhat unusual, though valid, transaction. It addresses the chip
590 * in write mode, but doesn't actually write any register address or data, then
591 * does a repeated start and reads data.
592 *
593 * If alen < 0, then we get this transaction:
594 * S Chip Rd [A] [data] A ... NA P
595 * The chip is addressed in read mode and then data is read. No register
596 * address is written first. This is perfectly valid on most devices and
597 * required on some (usually those that don't act like an array of registers).
Marek Vasut94cb8422011-09-22 09:22:12 +0000598 */
Peng Fan8262cb12015-05-15 07:29:12 +0800599static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
600 int alen, u8 *buf, int len)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100601{
Peng Fan8262cb12015-05-15 07:29:12 +0800602 int ret = 0;
603 u32 temp;
604 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
605 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
606 ulong base = i2c_bus->base;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100607
Peng Fan8262cb12015-05-15 07:29:12 +0800608 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
Troy Kisky752ac8f2012-07-19 08:18:04 +0000609 if (ret < 0)
Marek Vasut94cb8422011-09-22 09:22:12 +0000610 return ret;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100611
Nandor Hana51f9da2017-11-08 15:35:09 +0000612 if (alen >= 0) {
613 temp = readb(base + (I2CR << reg_shift));
614 temp |= I2CR_RSTA;
615 writeb(temp, base + (I2CR << reg_shift));
616 }
Peng Fan8262cb12015-05-15 07:29:12 +0800617
618 ret = tx_byte(i2c_bus, (chip << 1) | 1);
619 if (ret < 0) {
620 i2c_imx_stop(i2c_bus);
621 return ret;
Marek Vasut94cb8422011-09-22 09:22:12 +0000622 }
Peng Fan8262cb12015-05-15 07:29:12 +0800623
Trent Piepho9c896a92019-04-30 16:08:19 +0000624 ret = i2c_read_data(i2c_bus, chip, buf, len, true);
Peng Fan8262cb12015-05-15 07:29:12 +0800625
626 i2c_imx_stop(i2c_bus);
627 return ret;
628}
629
630/*
631 * Write data to I2C device
Trent Piepho15410ba2019-04-30 16:08:18 +0000632 *
633 * If alen > 0, we get this transaction:
634 * S Chip Wr [A] addr [A] data [A] ... [A] P
635 * An ordinary write register command.
636 *
637 * If alen == 0, then we get this:
638 * S Chip Wr [A] data [A] ... [A] P
639 * This is a simple I2C write.
640 *
641 * If alen < 0, then we get this:
642 * S data [A] ... [A] P
643 * This is most likely NOT something that should be used. It doesn't send the
644 * chip address first, so in effect, the first byte of data will be used as the
645 * address.
Peng Fan8262cb12015-05-15 07:29:12 +0800646 */
647static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
648 int alen, const u8 *buf, int len)
649{
650 int ret = 0;
651
652 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
653 if (ret < 0)
654 return ret;
655
656 ret = i2c_write_data(i2c_bus, chip, buf, len);
657
658 i2c_imx_stop(i2c_bus);
659
Marek Vasut94cb8422011-09-22 09:22:12 +0000660 return ret;
661}
Troy Kisky321a42b2012-07-19 08:18:08 +0000662
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200663#if !defined(I2C2_BASE_ADDR)
664#define I2C2_BASE_ADDR 0
Heiko Schocher5c4b1e92015-05-18 10:56:24 +0200665#endif
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200666
667#if !defined(I2C3_BASE_ADDR)
668#define I2C3_BASE_ADDR 0
669#endif
670
671#if !defined(I2C4_BASE_ADDR)
672#define I2C4_BASE_ADDR 0
673#endif
674
Sriram Dasha64aa192018-02-06 11:26:31 +0530675#if !defined(I2C5_BASE_ADDR)
676#define I2C5_BASE_ADDR 0
677#endif
678
679#if !defined(I2C6_BASE_ADDR)
680#define I2C6_BASE_ADDR 0
681#endif
682
683#if !defined(I2C7_BASE_ADDR)
684#define I2C7_BASE_ADDR 0
685#endif
686
687#if !defined(I2C8_BASE_ADDR)
688#define I2C8_BASE_ADDR 0
689#endif
690
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200691static struct mxc_i2c_bus mxc_i2c_buses[] = {
York Sunc4f047c2017-03-27 11:41:03 -0700692#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
Mingkai Hu0e58b512015-10-26 19:47:50 +0800693 defined(CONFIG_FSL_LAYERSCAPE)
Peng Fan8262cb12015-05-15 07:29:12 +0800694 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
695 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
696 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
697 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
Sriram Dasha64aa192018-02-06 11:26:31 +0530698 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
699 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
700 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
701 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
Troy Kiskyae447602012-07-19 08:18:18 +0000702#else
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200703 { 0, I2C1_BASE_ADDR, 0 },
704 { 1, I2C2_BASE_ADDR, 0 },
705 { 2, I2C3_BASE_ADDR, 0 },
706 { 3, I2C4_BASE_ADDR, 0 },
Sriram Dasha64aa192018-02-06 11:26:31 +0530707 { 4, I2C5_BASE_ADDR, 0 },
708 { 5, I2C6_BASE_ADDR, 0 },
709 { 6, I2C7_BASE_ADDR, 0 },
710 { 7, I2C8_BASE_ADDR, 0 },
Troy Kiskyae447602012-07-19 08:18:18 +0000711#endif
trema49f40a2013-09-21 18:13:35 +0200712};
713
Peng Fan8262cb12015-05-15 07:29:12 +0800714struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
Troy Kiskya23ab222012-07-19 08:18:19 +0000715{
Peng Fan8262cb12015-05-15 07:29:12 +0800716 return &mxc_i2c_buses[adap->hwadapnr];
Troy Kiskya23ab222012-07-19 08:18:19 +0000717}
Troy Kiskyb6f98262012-07-19 08:18:20 +0000718
trema49f40a2013-09-21 18:13:35 +0200719static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
720 uint addr, int alen, uint8_t *buffer,
721 int len)
Troy Kiskyae447602012-07-19 08:18:18 +0000722{
trema49f40a2013-09-21 18:13:35 +0200723 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kiskyae447602012-07-19 08:18:18 +0000724}
725
trema49f40a2013-09-21 18:13:35 +0200726static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
727 uint addr, int alen, uint8_t *buffer,
728 int len)
Troy Kiskyae447602012-07-19 08:18:18 +0000729{
trema49f40a2013-09-21 18:13:35 +0200730 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kiskyae447602012-07-19 08:18:18 +0000731}
732
733/*
Troy Kisky321a42b2012-07-19 08:18:08 +0000734 * Test if a chip at a given address responds (probe the chip)
735 */
trema49f40a2013-09-21 18:13:35 +0200736static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
Troy Kisky321a42b2012-07-19 08:18:08 +0000737{
trema49f40a2013-09-21 18:13:35 +0200738 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
Troy Kiskyae447602012-07-19 08:18:18 +0000739}
Peng Fan8262cb12015-05-15 07:29:12 +0800740
Peng Fan8262cb12015-05-15 07:29:12 +0800741void bus_i2c_init(int index, int speed, int unused,
742 int (*idle_bus_fn)(void *p), void *idle_bus_data)
Troy Kiskyae447602012-07-19 08:18:18 +0000743{
Peng Fan8262cb12015-05-15 07:29:12 +0800744 int ret;
745
746 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
747 debug("Error i2c index\n");
Troy Kiskyae447602012-07-19 08:18:18 +0000748 return;
Peng Fan8262cb12015-05-15 07:29:12 +0800749 }
750
Peng Fan23d4ee32020-05-01 22:08:35 +0800751 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
752 if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
753 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
754 (ulong)mxc_i2c_buses[index].base);
755 return;
756 }
757 }
758
Gong Qianyufd999082015-12-18 17:38:01 +0800759 /*
760 * Warning: Be careful to allow the assignment to a static
761 * variable here. This function could be called while U-Boot is
762 * still running in flash memory. So such assignment is equal
763 * to write data to flash without erasing.
764 */
765 if (idle_bus_fn)
766 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
767 if (idle_bus_data)
768 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
Peng Fan8262cb12015-05-15 07:29:12 +0800769
770 ret = enable_i2c_clk(1, index);
771 if (ret < 0) {
772 debug("I2C-%d clk fail to enable.\n", index);
773 return;
Troy Kiskyae447602012-07-19 08:18:18 +0000774 }
Peng Fan8262cb12015-05-15 07:29:12 +0800775
776 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
Troy Kiskyae447602012-07-19 08:18:18 +0000777}
778
779/*
Yuan Yaod40c8852016-06-08 18:24:51 +0800780 * Early init I2C for prepare read the clk through I2C.
781 */
782void i2c_early_init_f(void)
783{
784 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
785 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
786 & I2C_QUIRK_FLAG ? true : false;
787 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
788
789 /* Set I2C divider value */
790 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
791 /* Reset module */
792 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
793 writeb(0, base + (I2SR << reg_shift));
794 /* Enable I2C */
795 writeb(I2CR_IEN, base + (I2CR << reg_shift));
796}
797
798/*
Troy Kiskyae447602012-07-19 08:18:18 +0000799 * Init I2C Bus
800 */
trema49f40a2013-09-21 18:13:35 +0200801static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Troy Kiskyae447602012-07-19 08:18:18 +0000802{
Peng Fan8262cb12015-05-15 07:29:12 +0800803 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
Troy Kiskyae447602012-07-19 08:18:18 +0000804}
805
806/*
807 * Set I2C Speed
808 */
Peng Fan8262cb12015-05-15 07:29:12 +0800809static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
Troy Kiskyae447602012-07-19 08:18:18 +0000810{
trema49f40a2013-09-21 18:13:35 +0200811 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
Troy Kiskyae447602012-07-19 08:18:18 +0000812}
813
814/*
trema49f40a2013-09-21 18:13:35 +0200815 * Register mxc i2c adapters
Troy Kiskyae447602012-07-19 08:18:18 +0000816 */
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200817#ifdef CONFIG_SYS_I2C_MXC_I2C1
trema49f40a2013-09-21 18:13:35 +0200818U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
819 mxc_i2c_read, mxc_i2c_write,
820 mxc_i2c_set_bus_speed,
821 CONFIG_SYS_MXC_I2C1_SPEED,
822 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200823#endif
824
825#ifdef CONFIG_SYS_I2C_MXC_I2C2
trema49f40a2013-09-21 18:13:35 +0200826U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
827 mxc_i2c_read, mxc_i2c_write,
828 mxc_i2c_set_bus_speed,
829 CONFIG_SYS_MXC_I2C2_SPEED,
830 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200831#endif
832
York Sunf1a52162015-03-20 10:20:40 -0700833#ifdef CONFIG_SYS_I2C_MXC_I2C3
trema49f40a2013-09-21 18:13:35 +0200834U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
835 mxc_i2c_read, mxc_i2c_write,
836 mxc_i2c_set_bus_speed,
837 CONFIG_SYS_MXC_I2C3_SPEED,
838 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
839#endif
Peng Fan8262cb12015-05-15 07:29:12 +0800840
York Sunf1a52162015-03-20 10:20:40 -0700841#ifdef CONFIG_SYS_I2C_MXC_I2C4
842U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
843 mxc_i2c_read, mxc_i2c_write,
844 mxc_i2c_set_bus_speed,
845 CONFIG_SYS_MXC_I2C4_SPEED,
846 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
847#endif
Peng Fan8262cb12015-05-15 07:29:12 +0800848
Sriram Dasha64aa192018-02-06 11:26:31 +0530849#ifdef CONFIG_SYS_I2C_MXC_I2C5
850U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
851 mxc_i2c_read, mxc_i2c_write,
852 mxc_i2c_set_bus_speed,
853 CONFIG_SYS_MXC_I2C5_SPEED,
854 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
855#endif
856
857#ifdef CONFIG_SYS_I2C_MXC_I2C6
858U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
859 mxc_i2c_read, mxc_i2c_write,
860 mxc_i2c_set_bus_speed,
861 CONFIG_SYS_MXC_I2C6_SPEED,
862 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
863#endif
864
865#ifdef CONFIG_SYS_I2C_MXC_I2C7
866U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
867 mxc_i2c_read, mxc_i2c_write,
868 mxc_i2c_set_bus_speed,
869 CONFIG_SYS_MXC_I2C7_SPEED,
870 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
871#endif
872
873#ifdef CONFIG_SYS_I2C_MXC_I2C8
874U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
875 mxc_i2c_read, mxc_i2c_write,
876 mxc_i2c_set_bus_speed,
877 CONFIG_SYS_MXC_I2C8_SPEED,
878 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
879#endif
880
Peng Fan8262cb12015-05-15 07:29:12 +0800881#else
882
883static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
884{
885 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
886
887 return bus_i2c_set_bus_speed(i2c_bus, speed);
888}
889
890static int mxc_i2c_probe(struct udevice *bus)
891{
892 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
Peng Fan4f1a5812016-03-11 16:47:50 +0800893 const void *fdt = gd->fdt_blob;
Simon Glassdd79d6e2017-01-17 16:52:55 -0700894 int node = dev_of_offset(bus);
Peng Fan8262cb12015-05-15 07:29:12 +0800895 fdt_addr_t addr;
Peng Fan4f1a5812016-03-11 16:47:50 +0800896 int ret, ret2;
Peng Fan8262cb12015-05-15 07:29:12 +0800897
898 i2c_bus->driver_data = dev_get_driver_data(bus);
899
Simon Glassba1dea42017-05-17 17:18:05 -0600900 addr = devfdt_get_addr(bus);
Peng Fan8262cb12015-05-15 07:29:12 +0800901 if (addr == FDT_ADDR_T_NONE)
Simon Glassf44b4bf2017-09-17 16:54:53 -0600902 return -EINVAL;
Peng Fan8262cb12015-05-15 07:29:12 +0800903
Peng Fan23d4ee32020-05-01 22:08:35 +0800904 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
905 if (i2c_fused((ulong)addr)) {
906 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
907 (ulong)addr);
908 return -ENODEV;
909 }
910 }
911
Peng Fan8262cb12015-05-15 07:29:12 +0800912 i2c_bus->base = addr;
913 i2c_bus->index = bus->seq;
Peng Fan4f1a5812016-03-11 16:47:50 +0800914 i2c_bus->bus = bus;
Peng Fan8262cb12015-05-15 07:29:12 +0800915
916 /* Enable clk */
Peng Fan87ea5622019-08-08 01:43:30 +0000917#if CONFIG_IS_ENABLED(CLK)
918 ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
919 if (ret) {
920 printf("Failed to get i2c clk\n");
921 return ret;
922 }
923 ret = clk_enable(&i2c_bus->per_clk);
924 if (ret) {
925 printf("Failed to enable i2c clk\n");
926 return ret;
927 }
928#else
Peng Fan8262cb12015-05-15 07:29:12 +0800929 ret = enable_i2c_clk(1, bus->seq);
930 if (ret < 0)
931 return ret;
Peng Fan87ea5622019-08-08 01:43:30 +0000932#endif
Peng Fan8262cb12015-05-15 07:29:12 +0800933
Peng Fan4f1a5812016-03-11 16:47:50 +0800934 /*
935 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
936 * Use gpio to force bus idle when necessary.
937 */
Simon Glassb0ea7402016-10-02 17:59:28 -0600938 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
Peng Fan4f1a5812016-03-11 16:47:50 +0800939 if (ret < 0) {
Jagan Tekicac30062016-12-06 00:00:59 +0100940 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
Peng Fan4f1a5812016-03-11 16:47:50 +0800941 } else {
Simon Glass1d9af1f2017-05-30 21:47:09 -0600942 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
943 "scl-gpios", 0, &i2c_bus->scl_gpio,
944 GPIOD_IS_OUT);
945 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
946 "sda-gpios", 0, &i2c_bus->sda_gpio,
947 GPIOD_IS_OUT);
Peng Fan08eaa832017-12-29 15:06:08 +0800948 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
949 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
950 ret || ret2) {
Peng Fan4f1a5812016-03-11 16:47:50 +0800951 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
Simon Glassf44b4bf2017-09-17 16:54:53 -0600952 return -EINVAL;
Peng Fan4f1a5812016-03-11 16:47:50 +0800953 }
954 }
955
Peng Fan8262cb12015-05-15 07:29:12 +0800956 /*
957 * Pinmux settings are in board file now, until pinmux is supported,
958 * we can set pinmux here in probe function.
959 */
960
961 debug("i2c : controller bus %d at %lu , speed %d: ",
962 bus->seq, i2c_bus->base,
963 i2c_bus->speed);
964
965 return 0;
966}
967
Trent Piepho15410ba2019-04-30 16:08:18 +0000968/* Sends: S Addr Wr [A|NA] P */
Peng Fan8262cb12015-05-15 07:29:12 +0800969static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
970 u32 chip_flags)
971{
972 int ret;
973 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
974
975 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
976 if (ret < 0) {
977 debug("%s failed, ret = %d\n", __func__, ret);
978 return ret;
979 }
980
981 i2c_imx_stop(i2c_bus);
982
983 return 0;
984}
985
986static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
987{
988 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
989 int ret = 0;
990 ulong base = i2c_bus->base;
991 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
992 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Trent Piepho9c896a92019-04-30 16:08:19 +0000993 int read_mode;
Peng Fan8262cb12015-05-15 07:29:12 +0800994
Trent Piepho9c896a92019-04-30 16:08:19 +0000995 /* Here address len is set to -1 to not send any address at first.
996 * Otherwise i2c_init_transfer will send the chip address with write
997 * mode set. This is wrong if the 1st message is read.
Peng Fan8262cb12015-05-15 07:29:12 +0800998 */
Trent Piepho9c896a92019-04-30 16:08:19 +0000999 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
Peng Fan8262cb12015-05-15 07:29:12 +08001000 if (ret < 0) {
1001 debug("i2c_init_transfer error: %d\n", ret);
1002 return ret;
1003 }
1004
Trent Piepho9c896a92019-04-30 16:08:19 +00001005 read_mode = -1; /* So it's always different on the first message */
Peng Fan8262cb12015-05-15 07:29:12 +08001006 for (; nmsgs > 0; nmsgs--, msg++) {
Trent Piepho9c896a92019-04-30 16:08:19 +00001007 const int msg_is_read = !!(msg->flags & I2C_M_RD);
1008
1009 debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
1010 msg->len, msg_is_read ? 'R' : 'W');
1011
1012 if (msg_is_read != read_mode) {
1013 /* Send repeated start if not 1st message */
1014 if (read_mode != -1) {
1015 debug("i2c_xfer: [RSTART]\n");
Peng Fan8262cb12015-05-15 07:29:12 +08001016 ret = readb(base + (I2CR << reg_shift));
1017 ret |= I2CR_RSTA;
1018 writeb(ret, base + (I2CR << reg_shift));
Peng Fan8262cb12015-05-15 07:29:12 +08001019 }
Trent Piepho9c896a92019-04-30 16:08:19 +00001020 debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
1021 msg_is_read ? 'R' : 'W');
1022 ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
1023 if (ret < 0) {
1024 debug("i2c_xfer: [STOP]\n");
1025 i2c_imx_stop(i2c_bus);
1026 break;
1027 }
1028 read_mode = msg_is_read;
Peng Fan8262cb12015-05-15 07:29:12 +08001029 }
Trent Piepho9c896a92019-04-30 16:08:19 +00001030
1031 if (msg->flags & I2C_M_RD)
1032 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1033 msg->len, nmsgs == 1 ||
1034 (msg->flags & I2C_M_STOP));
1035 else
1036 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1037 msg->len);
1038
1039 if (ret < 0)
1040 break;
Peng Fan8262cb12015-05-15 07:29:12 +08001041 }
1042
1043 if (ret)
1044 debug("i2c_write: error sending\n");
1045
1046 i2c_imx_stop(i2c_bus);
1047
1048 return ret;
1049}
1050
1051static const struct dm_i2c_ops mxc_i2c_ops = {
1052 .xfer = mxc_i2c_xfer,
1053 .probe_chip = mxc_i2c_probe_chip,
1054 .set_bus_speed = mxc_i2c_set_bus_speed,
1055};
1056
1057static const struct udevice_id mxc_i2c_ids[] = {
1058 { .compatible = "fsl,imx21-i2c", },
1059 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
1060 {}
1061};
1062
1063U_BOOT_DRIVER(i2c_mxc) = {
1064 .name = "i2c_mxc",
1065 .id = UCLASS_I2C,
1066 .of_match = mxc_i2c_ids,
1067 .probe = mxc_i2c_probe,
1068 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
1069 .ops = &mxc_i2c_ops,
Biwen Li41a5abc2019-12-31 15:33:39 +08001070 .flags = DM_FLAG_PRE_RELOC,
Peng Fan8262cb12015-05-15 07:29:12 +08001071};
1072#endif