Peng Fan | 2d9bd93 | 2019-07-31 07:01:54 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved. |
| 4 | * Copyright 2019 NXP |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <malloc.h> |
| 10 | #include <clk-uclass.h> |
| 11 | #include <dm/device.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 12 | #include <dm/devres.h> |
Peng Fan | 2d9bd93 | 2019-07-31 07:01:54 +0000 | [diff] [blame] | 13 | #include <linux/clk-provider.h> |
| 14 | #include <clk.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 15 | #include <linux/err.h> |
Peng Fan | 2d9bd93 | 2019-07-31 07:01:54 +0000 | [diff] [blame] | 16 | |
| 17 | #include "clk.h" |
| 18 | |
| 19 | #define UBOOT_DM_CLK_COMPOSITE "clk_composite" |
| 20 | |
| 21 | static u8 clk_composite_get_parent(struct clk *clk) |
| 22 | { |
| 23 | struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? |
| 24 | (struct clk *)dev_get_clk_ptr(clk->dev) : clk); |
| 25 | struct clk *mux = composite->mux; |
| 26 | |
| 27 | return clk_mux_get_parent(mux); |
| 28 | } |
| 29 | |
| 30 | static int clk_composite_set_parent(struct clk *clk, struct clk *parent) |
| 31 | { |
| 32 | struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? |
| 33 | (struct clk *)dev_get_clk_ptr(clk->dev) : clk); |
| 34 | const struct clk_ops *mux_ops = composite->mux_ops; |
| 35 | struct clk *mux = composite->mux; |
| 36 | |
| 37 | return mux_ops->set_parent(mux, parent); |
| 38 | } |
| 39 | |
| 40 | static unsigned long clk_composite_recalc_rate(struct clk *clk) |
| 41 | { |
| 42 | struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? |
| 43 | (struct clk *)dev_get_clk_ptr(clk->dev) : clk); |
| 44 | const struct clk_ops *rate_ops = composite->rate_ops; |
| 45 | struct clk *rate = composite->rate; |
| 46 | |
| 47 | return rate_ops->get_rate(rate); |
| 48 | } |
| 49 | |
| 50 | static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate) |
| 51 | { |
| 52 | struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? |
| 53 | (struct clk *)dev_get_clk_ptr(clk->dev) : clk); |
| 54 | const struct clk_ops *rate_ops = composite->rate_ops; |
| 55 | struct clk *clk_rate = composite->rate; |
| 56 | |
| 57 | return rate_ops->set_rate(clk_rate, rate); |
| 58 | } |
| 59 | |
| 60 | static int clk_composite_enable(struct clk *clk) |
| 61 | { |
| 62 | struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? |
| 63 | (struct clk *)dev_get_clk_ptr(clk->dev) : clk); |
| 64 | const struct clk_ops *gate_ops = composite->gate_ops; |
| 65 | struct clk *gate = composite->gate; |
| 66 | |
| 67 | return gate_ops->enable(gate); |
| 68 | } |
| 69 | |
| 70 | static int clk_composite_disable(struct clk *clk) |
| 71 | { |
| 72 | struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? |
| 73 | (struct clk *)dev_get_clk_ptr(clk->dev) : clk); |
| 74 | const struct clk_ops *gate_ops = composite->gate_ops; |
| 75 | struct clk *gate = composite->gate; |
| 76 | |
| 77 | gate_ops->disable(gate); |
| 78 | |
| 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | struct clk_ops clk_composite_ops = { |
| 83 | /* This will be set according to clk_register_composite */ |
| 84 | }; |
| 85 | |
| 86 | struct clk *clk_register_composite(struct device *dev, const char *name, |
| 87 | const char * const *parent_names, |
| 88 | int num_parents, struct clk *mux, |
| 89 | const struct clk_ops *mux_ops, |
| 90 | struct clk *rate, |
| 91 | const struct clk_ops *rate_ops, |
| 92 | struct clk *gate, |
| 93 | const struct clk_ops *gate_ops, |
| 94 | unsigned long flags) |
| 95 | { |
| 96 | struct clk *clk; |
| 97 | struct clk_composite *composite; |
| 98 | int ret; |
| 99 | struct clk_ops *composite_ops = &clk_composite_ops; |
| 100 | |
| 101 | composite = kzalloc(sizeof(*composite), GFP_KERNEL); |
| 102 | if (!composite) |
| 103 | return ERR_PTR(-ENOMEM); |
| 104 | |
| 105 | if (mux && mux_ops) { |
| 106 | composite->mux = mux; |
| 107 | composite->mux_ops = mux_ops; |
| 108 | if (mux_ops->set_parent) |
| 109 | composite_ops->set_parent = clk_composite_set_parent; |
| 110 | mux->data = (ulong)composite; |
| 111 | } |
| 112 | |
| 113 | if (rate && rate_ops) { |
| 114 | if (!rate_ops->get_rate) { |
| 115 | clk = ERR_PTR(-EINVAL); |
| 116 | goto err; |
| 117 | } |
| 118 | composite_ops->get_rate = clk_composite_recalc_rate; |
| 119 | |
| 120 | /* .set_rate requires either .round_rate or .determine_rate */ |
| 121 | if (rate_ops->set_rate) |
| 122 | composite_ops->set_rate = clk_composite_set_rate; |
| 123 | |
| 124 | composite->rate = rate; |
| 125 | composite->rate_ops = rate_ops; |
| 126 | rate->data = (ulong)composite; |
| 127 | } |
| 128 | |
| 129 | if (gate && gate_ops) { |
| 130 | if (!gate_ops->enable || !gate_ops->disable) { |
| 131 | clk = ERR_PTR(-EINVAL); |
| 132 | goto err; |
| 133 | } |
| 134 | |
| 135 | composite->gate = gate; |
| 136 | composite->gate_ops = gate_ops; |
| 137 | composite_ops->enable = clk_composite_enable; |
| 138 | composite_ops->disable = clk_composite_disable; |
| 139 | gate->data = (ulong)composite; |
| 140 | } |
| 141 | |
| 142 | clk = &composite->clk; |
| 143 | ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name, |
| 144 | parent_names[clk_composite_get_parent(clk)]); |
| 145 | if (ret) { |
| 146 | clk = ERR_PTR(ret); |
| 147 | goto err; |
| 148 | } |
| 149 | |
| 150 | return clk; |
| 151 | |
| 152 | err: |
| 153 | kfree(composite); |
| 154 | return clk; |
| 155 | } |
| 156 | |
| 157 | U_BOOT_DRIVER(clk_composite) = { |
| 158 | .name = UBOOT_DM_CLK_COMPOSITE, |
| 159 | .id = UCLASS_CLK, |
| 160 | .ops = &clk_composite_ops, |
| 161 | .flags = DM_FLAG_PRE_RELOC, |
| 162 | }; |