blob: f02642aecec4df937a7ce2033b9b3d7705027bb4 [file] [log] [blame]
Valentin Longchampc98bf292013-10-18 11:47:24 +02001/*
2 * (C) Copyright 2013 Keymile AG
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
4 *
5 * Copyright 2011,2012 Freescale Semiconductor, Inc.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <command.h>
12#include <netdev.h>
13#include <linux/compiler.h>
14#include <asm/mmu.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17#include <asm/immap_85xx.h>
18#include <asm/fsl_law.h>
19#include <asm/fsl_serdes.h>
20#include <asm/fsl_portals.h>
21#include <asm/fsl_liodn.h>
22#include <fm_eth.h>
23
24#include "../common/common.h"
25#include "kmp204x.h"
26
27DECLARE_GLOBAL_DATA_PTR;
28
29int checkboard(void)
30{
31 printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
32
33 return 0;
34}
35
36/* TODO: implement the I2C deblocking function */
37int i2c_make_abort(void)
38{
39 return 1;
40}
41
42#define ZL30158_RST 8
43#define ZL30343_RST 9
44
45int board_early_init_f(void)
46{
47 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48
49 /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
50 setbits_be32(&gur->ddrclkdr, 0x001f000f);
51
52 /* take the Zarlinks out of reset as soon as possible */
53 qrio_prst(ZL30158_RST, false, false);
54 qrio_prst(ZL30343_RST, false, false);
55
56 /* and set their reset to power-up only */
57 qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
58 qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
59
60 return 0;
61}
62
63int board_early_init_r(void)
64{
65 /* Flush d-cache and invalidate i-cache of any FLASH data */
66 flush_dcache();
67 invalidate_icache();
68
69 set_liodns();
70 setup_portals();
71
72 return 0;
73}
74
75unsigned long get_board_sys_clk(unsigned long dummy)
76{
77 return 66666666;
78}
79
80#define WDMASK_OFF 0x16
81
82static void qrio_wdmask(u8 bit, bool wden)
83{
84 u16 wdmask;
85 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
86
87 wdmask = in_be16(qrio_base + WDMASK_OFF);
88
89 if (wden)
90 wdmask |= (1 << bit);
91 else
92 wdmask &= ~(1 << bit);
93
94 out_be16(qrio_base + WDMASK_OFF, wdmask);
95}
96
97#define PRST_OFF 0x1a
98
99void qrio_prst(u8 bit, bool en, bool wden)
100{
101 u16 prst;
102 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
103
104 qrio_wdmask(bit, wden);
105
106 prst = in_be16(qrio_base + PRST_OFF);
107
108 if (en)
109 prst &= ~(1 << bit);
110 else
111 prst |= (1 << bit);
112
113 out_be16(qrio_base + PRST_OFF, prst);
114}
115
116#define PRSTCFG_OFF 0x1c
117
118void qrio_prstcfg(u8 bit, u8 mode)
119{
120 u32 prstcfg;
121 u8 i;
122 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
123
124 prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
125
126 for (i = 0; i < 2; i++) {
127 if (mode & (1<<i))
128 set_bit(2*bit+i, &prstcfg);
129 else
130 clear_bit(2*bit+i, &prstcfg);
131 }
132
133 out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
134}
135
136
137#define BOOTCOUNT_OFF 0x12
138
139void bootcount_store(ulong counter)
140{
141 u8 val;
142 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
143
144 val = (counter <= 255) ? (u8)counter : 255;
145 out_8(qrio_base + BOOTCOUNT_OFF, val);
146}
147
148ulong bootcount_load(void)
149{
150 u8 val;
151 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
152 val = in_8(qrio_base + BOOTCOUNT_OFF);
153 return val;
154}
155
156#define NUM_SRDS_BANKS 2
157#define PHY_RST 15
158
159int misc_init_r(void)
160{
161 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
162 u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
163 SRDS_PLLCR0_RFCK_SEL_125};
164 unsigned int i;
165
166 /* check SERDES reference clocks */
167 for (i = 0; i < NUM_SRDS_BANKS; i++) {
168 u32 actual = in_be32(&regs->bank[i].pllcr0);
169 actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
170 if (actual != expected[i]) {
171 printf("Warning: SERDES bank %u expects reference \
172 clock %sMHz, but actual is %sMHz\n", i + 1,
173 serdes_clock_to_string(expected[i]),
174 serdes_clock_to_string(actual));
175 }
176 }
177
178 /* take the mgmt eth phy out of reset */
179 qrio_prst(PHY_RST, false, false);
180
181 return 0;
182}
183
184#if defined(CONFIG_HUSH_INIT_VAR)
185int hush_init_var(void)
186{
187 ivm_read_eeprom();
188 return 0;
189}
190#endif
191
192#if defined(CONFIG_LAST_STAGE_INIT)
193int last_stage_init(void)
194{
195 set_km_env();
196 return 0;
197}
198#endif
199
200#ifdef CONFIG_SYS_DPAA_FMAN
201void fdt_fixup_fman_mac_addresses(void *blob)
202{
203 int node, i, ret;
204 char *tmp, *end;
205 unsigned char mac_addr[6];
206
207 /* get the mac addr from env */
208 tmp = getenv("ethaddr");
209 if (!tmp) {
210 printf("ethaddr env variable not defined\n");
211 return;
212 }
213 for (i = 0; i < 6; i++) {
214 mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
215 if (tmp)
216 tmp = (*end) ? end+1 : end;
217 }
218
219 /* find the correct fdt ethernet path and correct it */
220 node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
221 if (node < 0) {
222 printf("no /soc/fman/ethernet path offset\n");
223 return;
224 }
225 ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
226 if (ret) {
227 printf("error setting local-mac-address property\n");
228 return;
229 }
230}
231#endif
232
233void ft_board_setup(void *blob, bd_t *bd)
234{
235 phys_addr_t base;
236 phys_size_t size;
237
238 ft_cpu_setup(blob, bd);
239
240 base = getenv_bootm_low();
241 size = getenv_bootm_size();
242
243 fdt_fixup_memory(blob, (u64)base, (u64)size);
244
245#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
246 fdt_fixup_dr_usb(blob, bd);
247#endif
248
249#ifdef CONFIG_PCI
250 pci_of_setup(blob, bd);
251#endif
252
253 fdt_fixup_liodn(blob);
254#ifdef CONFIG_SYS_DPAA_FMAN
255 fdt_fixup_fman_ethernet(blob);
256 fdt_fixup_fman_mac_addresses(blob);
257#endif
258}