Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016 Stefano Babic <sbabic@denx.de> |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * Please note: there are two version of the board |
| 8 | * one with NAND and the other with eMMC. |
| 9 | * Both NAND and eMMC cannot be set because they share the |
| 10 | * same pins (SD4) |
| 11 | */ |
| 12 | #include <common.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 13 | #include <init.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 14 | #include <net.h> |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 15 | #include <asm/arch/crm_regs.h> |
| 16 | #include <asm/arch/mx6-ddr.h> |
Stefano Babic | 33731bc | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 17 | #include <asm/mach-imx/boot_mode.h> |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 18 | #include <asm/arch/sys_proto.h> |
Niel Fourie | 8ee1907 | 2020-05-19 14:01:43 +0200 | [diff] [blame^] | 19 | #include <dm.h> |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 20 | |
| 21 | DECLARE_GLOBAL_DATA_PTR; |
| 22 | |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 23 | #define IMX6Q_DRIVE_STRENGTH 0x30 |
| 24 | |
| 25 | int dram_init(void) |
| 26 | { |
| 27 | gd->ram_size = imx_ddr_size(); |
| 28 | return 0; |
| 29 | } |
| 30 | |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 31 | int board_mmc_get_env_dev(int devno) |
| 32 | { |
| 33 | return devno - 1; |
| 34 | } |
| 35 | |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 36 | #ifdef CONFIG_CMD_NAND |
| 37 | static void setup_gpmi_nand(void) |
| 38 | { |
| 39 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 40 | |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 41 | /* gate ENFC_CLK_ROOT clock first,before clk source switch */ |
| 42 | clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); |
| 43 | |
| 44 | /* config gpmi and bch clock to 100 MHz */ |
| 45 | clrsetbits_le32(&mxc_ccm->cs2cdr, |
| 46 | MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | |
| 47 | MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | |
| 48 | MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, |
| 49 | MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | |
| 50 | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | |
| 51 | MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); |
| 52 | |
| 53 | /* enable ENFC_CLK_ROOT clock */ |
| 54 | setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); |
| 55 | |
| 56 | /* enable gpmi and bch clock gating */ |
| 57 | setbits_le32(&mxc_ccm->CCGR4, |
| 58 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| 59 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| 60 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| 61 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| 62 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); |
| 63 | |
| 64 | /* enable apbh clock gating */ |
| 65 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |
| 66 | } |
| 67 | #endif |
| 68 | |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 69 | int board_init(void) |
| 70 | { |
| 71 | /* address of boot parameters */ |
| 72 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 73 | |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 74 | #ifdef CONFIG_CMD_NAND |
| 75 | setup_gpmi_nand(); |
| 76 | #endif |
| 77 | return 0; |
| 78 | } |
| 79 | |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 80 | #ifdef CONFIG_CMD_BMODE |
| 81 | /* |
| 82 | * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 |
| 83 | * see Table 8-11 and Table 5-9 |
| 84 | * BOOT_CFG1[7] = 1 (boot from NAND) |
| 85 | * BOOT_CFG1[5] = 0 - raw NAND |
| 86 | * BOOT_CFG1[4] = 0 - default pad settings |
| 87 | * BOOT_CFG1[3:2] = 00 - devices = 1 |
| 88 | * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 |
| 89 | * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 |
| 90 | * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 |
| 91 | * BOOT_CFG2[0] = 0 - Reset time 12ms |
| 92 | */ |
| 93 | static const struct boot_mode board_boot_modes[] = { |
| 94 | /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ |
| 95 | {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)}, |
| 96 | {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, |
| 97 | {NULL, 0}, |
| 98 | }; |
| 99 | #endif |
| 100 | |
| 101 | int board_late_init(void) |
| 102 | { |
| 103 | #ifdef CONFIG_CMD_BMODE |
| 104 | add_board_boot_modes(board_boot_modes); |
| 105 | #endif |
| 106 | |
| 107 | return 0; |
| 108 | } |
| 109 | |
| 110 | #ifdef CONFIG_SPL_BUILD |
| 111 | #include <spl.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 112 | #include <linux/libfdt.h> |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 113 | |
| 114 | static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { |
| 115 | .dram_sdclk_0 = 0x00000030, |
| 116 | .dram_sdclk_1 = 0x00000030, |
| 117 | .dram_cas = 0x00000030, |
| 118 | .dram_ras = 0x00000030, |
| 119 | .dram_reset = 0x00000030, |
| 120 | .dram_sdcke0 = 0x00000030, |
| 121 | .dram_sdcke1 = 0x00000030, |
| 122 | .dram_sdba2 = 0x00000000, |
| 123 | .dram_sdodt0 = 0x00000030, |
| 124 | .dram_sdodt1 = 0x00000030, |
| 125 | .dram_sdqs0 = 0x00000030, |
| 126 | .dram_sdqs1 = 0x00000030, |
| 127 | .dram_sdqs2 = 0x00000030, |
| 128 | .dram_sdqs3 = 0x00000030, |
| 129 | .dram_sdqs4 = 0x00000030, |
| 130 | .dram_sdqs5 = 0x00000030, |
| 131 | .dram_sdqs6 = 0x00000030, |
| 132 | .dram_sdqs7 = 0x00000030, |
| 133 | .dram_dqm0 = 0x00000030, |
| 134 | .dram_dqm1 = 0x00000030, |
| 135 | .dram_dqm2 = 0x00000030, |
| 136 | .dram_dqm3 = 0x00000030, |
| 137 | .dram_dqm4 = 0x00000030, |
| 138 | .dram_dqm5 = 0x00000030, |
| 139 | .dram_dqm6 = 0x00000030, |
| 140 | .dram_dqm7 = 0x00000030, |
| 141 | }; |
| 142 | |
| 143 | static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { |
| 144 | .grp_ddr_type = 0x000C0000, |
| 145 | .grp_ddrmode_ctl = 0x00020000, |
| 146 | .grp_ddrpke = 0x00000000, |
| 147 | .grp_addds = IMX6Q_DRIVE_STRENGTH, |
| 148 | .grp_ctlds = IMX6Q_DRIVE_STRENGTH, |
| 149 | .grp_ddrmode = 0x00020000, |
| 150 | .grp_b0ds = IMX6Q_DRIVE_STRENGTH, |
| 151 | .grp_b1ds = IMX6Q_DRIVE_STRENGTH, |
| 152 | .grp_b2ds = IMX6Q_DRIVE_STRENGTH, |
| 153 | .grp_b3ds = IMX6Q_DRIVE_STRENGTH, |
| 154 | .grp_b4ds = IMX6Q_DRIVE_STRENGTH, |
| 155 | .grp_b5ds = IMX6Q_DRIVE_STRENGTH, |
| 156 | .grp_b6ds = IMX6Q_DRIVE_STRENGTH, |
| 157 | .grp_b7ds = IMX6Q_DRIVE_STRENGTH, |
| 158 | }; |
| 159 | |
| 160 | static const struct mx6_mmdc_calibration mx6_mmcd_calib = { |
| 161 | .p0_mpwldectrl0 = 0x00140014, |
| 162 | .p0_mpwldectrl1 = 0x000A0015, |
| 163 | .p1_mpwldectrl0 = 0x000A001E, |
| 164 | .p1_mpwldectrl1 = 0x000A0015, |
| 165 | .p0_mpdgctrl0 = 0x43080314, |
| 166 | .p0_mpdgctrl1 = 0x02680300, |
| 167 | .p1_mpdgctrl0 = 0x430C0318, |
| 168 | .p1_mpdgctrl1 = 0x03000254, |
| 169 | .p0_mprddlctl = 0x3A323234, |
| 170 | .p1_mprddlctl = 0x3E3C3242, |
| 171 | .p0_mpwrdlctl = 0x2A2E3632, |
| 172 | .p1_mpwrdlctl = 0x3C323E34, |
| 173 | }; |
| 174 | |
| 175 | static struct mx6_ddr3_cfg mem_ddr = { |
| 176 | .mem_speed = 1600, |
| 177 | .density = 2, |
| 178 | .width = 16, |
| 179 | .banks = 8, |
| 180 | .rowaddr = 14, |
| 181 | .coladdr = 10, |
| 182 | .pagesz = 2, |
| 183 | .trcd = 1375, |
| 184 | .trcmin = 4875, |
| 185 | .trasmin = 3500, |
| 186 | .SRT = 1, |
| 187 | }; |
| 188 | |
| 189 | static void ccgr_init(void) |
| 190 | { |
| 191 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 192 | |
| 193 | writel(0x00C03F3F, &ccm->CCGR0); |
| 194 | writel(0x0030FC03, &ccm->CCGR1); |
| 195 | writel(0x0FFFC000, &ccm->CCGR2); |
| 196 | writel(0x3FF00000, &ccm->CCGR3); |
| 197 | writel(0x00FFF300, &ccm->CCGR4); |
| 198 | writel(0x0F0000C3, &ccm->CCGR5); |
| 199 | writel(0x000003FF, &ccm->CCGR6); |
| 200 | } |
| 201 | |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 202 | static void spl_dram_init(void) |
| 203 | { |
| 204 | struct mx6_ddr_sysinfo sysinfo = { |
| 205 | /* width of data bus:0=16,1=32,2=64 */ |
| 206 | .dsize = 2, |
| 207 | /* config for full 4GB range so that get_mem_size() works */ |
| 208 | .cs_density = 32, /* 32Gb per CS */ |
| 209 | /* single chip select */ |
| 210 | .ncs = 1, |
| 211 | .cs1_mirror = 0, |
| 212 | .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ |
| 213 | .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ |
| 214 | .walat = 1, /* Write additional latency */ |
| 215 | .ralat = 5, /* Read additional latency */ |
| 216 | .mif3_mode = 3, /* Command prediction working mode */ |
| 217 | .bi_on = 1, /* Bank interleaving enabled */ |
| 218 | .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
| 219 | .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
| 220 | .ddr_type = DDR_TYPE_DDR3, |
Fabio Estevam | cb3c121 | 2016-08-29 20:37:15 -0300 | [diff] [blame] | 221 | .refsel = 1, /* Refresh cycles at 32KHz */ |
| 222 | .refr = 7, /* 8 refresh commands per refresh cycle */ |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 223 | }; |
| 224 | |
| 225 | mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
| 226 | mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); |
| 227 | } |
| 228 | |
| 229 | void board_boot_order(u32 *spl_boot_list) |
| 230 | { |
| 231 | spl_boot_list[0] = spl_boot_device(); |
| 232 | printf("Boot device %x\n", spl_boot_list[0]); |
| 233 | switch (spl_boot_list[0]) { |
| 234 | case BOOT_DEVICE_SPI: |
| 235 | spl_boot_list[1] = BOOT_DEVICE_UART; |
| 236 | break; |
| 237 | case BOOT_DEVICE_MMC1: |
| 238 | spl_boot_list[1] = BOOT_DEVICE_SPI; |
| 239 | spl_boot_list[2] = BOOT_DEVICE_UART; |
| 240 | break; |
| 241 | default: |
| 242 | printf("Boot device %x\n", spl_boot_list[0]); |
| 243 | } |
| 244 | } |
| 245 | |
| 246 | void board_init_f(ulong dummy) |
| 247 | { |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 248 | /* setup clock gating */ |
| 249 | ccgr_init(); |
| 250 | |
| 251 | /* setup AIPS and disable watchdog */ |
| 252 | arch_cpu_init(); |
| 253 | |
| 254 | /* setup AXI */ |
| 255 | gpr_init(); |
| 256 | |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 257 | /* setup GP timer */ |
| 258 | timer_init(); |
| 259 | |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 260 | /* DDR initialization */ |
| 261 | spl_dram_init(); |
| 262 | |
| 263 | /* Clear the BSS. */ |
| 264 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 265 | |
Niel Fourie | 8ee1907 | 2020-05-19 14:01:43 +0200 | [diff] [blame^] | 266 | /* Enable device tree and early DM support*/ |
| 267 | spl_early_init(); |
| 268 | |
| 269 | /* UART clocks enabled and gd valid - init serial console */ |
| 270 | preloader_console_init(); |
| 271 | } |
| 272 | |
| 273 | /* |
| 274 | * Manually probe the SPI bus devices, as this does not happen when the |
| 275 | * SPI Flash is probed, which then fails to find the bus. |
| 276 | */ |
| 277 | void spl_board_init(void) |
| 278 | { |
| 279 | struct udevice *udev; |
| 280 | int ret = uclass_get_device_by_name(UCLASS_SPI, "spi@2008000", &udev); |
| 281 | |
| 282 | if (ret) { |
| 283 | printf("SPI bus probe failed, err = %d\n", ret); |
| 284 | }; |
Stefano Babic | 17b6037 | 2016-06-08 10:50:20 +0200 | [diff] [blame] | 285 | } |
| 286 | #endif |