| Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <config.h> |
| 8 | #include <common.h> |
| 9 | #include <spl.h> |
| 10 | #include <dm.h> |
| 11 | #include <ram.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <post.h> |
| 14 | #include <power/pmic.h> |
| 15 | #include <power/stpmu1.h> |
| 16 | #include <asm/arch/ddr.h> |
| 17 | |
| 18 | void spl_board_init(void) |
| 19 | { |
| 20 | /* Keep vdd on during the reset cycle */ |
| 21 | #if defined(CONFIG_PMIC_STPMU1) && defined(CONFIG_SPL_POWER_SUPPORT) |
| 22 | struct udevice *dev; |
| 23 | int ret; |
| 24 | |
| 25 | ret = uclass_get_device_by_driver(UCLASS_PMIC, |
| 26 | DM_GET_DRIVER(pmic_stpmu1), &dev); |
| 27 | if (!ret) |
| 28 | pmic_clrsetbits(dev, |
| 29 | STPMU1_MASK_RESET_BUCK, |
| 30 | STPMU1_MASK_RESET_BUCK3, |
| 31 | STPMU1_MASK_RESET_BUCK3); |
| 32 | #endif |
| 33 | } |