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Masahiro Yamada92b8c2f2016-01-12 16:36:38 +09001menu "Clock"
2
Simon Glass36ad2342015-06-23 15:39:15 -06003config CLK
4 bool "Enable clock driver support"
5 depends on DM
6 help
7 This allows drivers to be provided for clock generators, including
8 oscillators and PLLs. Devices can use a common clock API to request
9 a particular clock rate and check on available clocks. Clocks can
10 feed into other clocks in a tree structure, with multiplexers to
11 choose the source for each clock.
12
Masahiro Yamadab16de452015-08-12 07:31:46 +090013config SPL_CLK
Simon Glass36ad2342015-06-23 15:39:15 -060014 bool "Enable clock support in SPL"
Wenyou Yange4cf4132017-07-31 15:21:57 +080015 depends on CLK && SPL && SPL_DM
Simon Glass36ad2342015-06-23 15:39:15 -060016 help
17 The clock subsystem adds a small amount of overhead to the image.
18 If this is acceptable and you have a need to use clock drivers in
19 SPL, enable this option. It might provide a cleaner interface to
20 setting up clocks within SPL, and allows the same drivers to be
21 used as U-Boot proper.
Masahiro Yamada92b8c2f2016-01-12 16:36:38 +090022
Philipp Tomsich592c3db2017-06-29 01:45:01 +020023config TPL_CLK
24 bool "Enable clock support in TPL"
25 depends on CLK && TPL_DM
26 help
27 The clock subsystem adds a small amount of overhead to the image.
28 If this is acceptable and you have a need to use clock drivers in
29 SPL, enable this option. It might provide a cleaner interface to
30 setting up clocks within TPL, and allows the same drivers to be
31 used as U-Boot proper.
32
Simon Glasse7ca7da2022-04-30 00:56:53 -060033config VPL_CLK
34 bool "Enable clock support in VPL"
35 depends on CLK && VPL_DM
36 help
37 The clock subsystem adds a small amount of overhead to the image.
38 If this is acceptable and you have a need to use clock drivers in
39 SPL, enable this option. It might provide a cleaner interface to
40 setting up clocks within TPL, and allows the same drivers to be
41 used as U-Boot proper.
42
43config CLK_BCM6345
44 bool "Clock controller driver for BCM6345"
45 depends on CLK && ARCH_BMIPS
46 default y
47 help
48 This clock driver adds support for enabling and disabling peripheral
49 clocks on BCM6345 SoCs. HW has no rate changing capabilities.
50
51config CLK_BOSTON
52 def_bool y if TARGET_BOSTON
53 depends on CLK
54 select REGMAP
55 select SYSCON
56 help
57 Enable this to support the clocks
58
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020059config SPL_CLK_CCF
60 bool "SPL Common Clock Framework [CCF] support "
Adam Fordac4d80e2019-08-24 13:50:34 -050061 depends on SPL
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020062 help
63 Enable this option if you want to (re-)use the Linux kernel's Common
64 Clock Framework [CCF] code in U-Boot's SPL.
65
Peng Fan2d9bd932019-07-31 07:01:54 +000066config SPL_CLK_COMPOSITE_CCF
67 bool "SPL Common Clock Framework [CCF] composite clk support "
68 depends on SPL_CLK_CCF
69 help
70 Enable this option if you want to (re-)use the Linux kernel's Common
71 Clock Framework [CCF] composite code in U-Boot's SPL.
72
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020073config CLK_CCF
74 bool "Common Clock Framework [CCF] support "
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020075 help
76 Enable this option if you want to (re-)use the Linux kernel's Common
77 Clock Framework [CCF] code in U-Boot's clock driver.
78
Peng Fan2d9bd932019-07-31 07:01:54 +000079config CLK_COMPOSITE_CCF
80 bool "Common Clock Framework [CCF] composite clk support "
81 depends on CLK_CCF
82 help
83 Enable this option if you want to (re-)use the Linux kernel's Common
84 Clock Framework [CCF] composite code in U-Boot's clock driver.
85
Sean Andersond1f48b52021-12-15 11:36:19 -050086config CLK_BCM6345
87 bool "Clock controller driver for BCM6345"
88 depends on CLK && ARCH_BMIPS
89 default y
90 help
91 This clock driver adds support for enabling and disabling peripheral
92 clocks on BCM6345 SoCs. HW has no rate changing capabilities.
93
94config CLK_BOSTON
95 def_bool y if TARGET_BOSTON
96 depends on CLK
97 select REGMAP
98 select SYSCON
99 help
100 Enable this to support the clocks
101
102config CLK_CDCE9XX
103 bool "Enable CDCD9XX clock driver"
104 depends on CLK
105 help
106 Enable the clock synthesizer driver for CDCE913/925/937/949
107 series of chips.
108
Sean Anderson35b37542021-12-15 11:36:20 -0500109config CLK_ICS8N3QV01
Sean Andersond1f48b52021-12-15 11:36:19 -0500110 bool "Enable ICS8N3QV01 VCXO driver"
111 depends on CLK
112 help
113 Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled
114 Crystal Oscillator). The output frequency can be programmed via an
115 I2C interface.
116
Simon Glass6eb4e3c2020-02-06 09:54:53 -0700117config CLK_INTEL
118 bool "Enable clock driver for Intel x86"
119 depends on CLK && X86
120 help
121 This provides very basic support for clocks on Intel SoCs. The driver
122 is barely used at present but could be expanded as needs arise.
123 Much clock configuration in U-Boot is either set up by the FSP, or
124 set up by U-Boot itself but only statically. Thus the driver does not
125 support changing clock rates, only querying them.
126
Sean Andersond1f48b52021-12-15 11:36:19 -0500127config CLK_K210
128 bool "Clock support for Kendryte K210"
129 depends on CLK
130 help
131 This enables support clock driver for Kendryte K210 platforms.
132
133config CLK_K210_SET_RATE
134 bool "Enable setting the Kendryte K210 PLL rate"
135 depends on CLK_K210
136 help
137 Add functionality to calculate new rates for K210 PLLs. Enabling this
138 feature adds around 1K to U-Boot's final size.
139
140config CLK_MPC83XX
141 bool "Enable MPC83xx clock driver"
142 depends on CLK
143 help
144 Support for the clock driver of the MPC83xx series of SoCs.
145
Stefan Roese560b07f2020-07-30 13:56:16 +0200146config CLK_OCTEON
147 bool "Clock controller driver for Marvell MIPS Octeon"
148 depends on CLK && ARCH_OCTEON
149 default y
150 help
151 Enable this to support the clocks on Octeon MIPS platforms.
152
Sean Andersond1f48b52021-12-15 11:36:19 -0500153config SANDBOX_CLK_CCF
154 bool "Sandbox Common Clock Framework [CCF] support "
155 depends on SANDBOX
156 select CLK_CCF
157 help
158 Enable this option if you want to test the Linux kernel's Common
159 Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
160
161config CLK_SCMI
162 bool "Enable SCMI clock driver"
163 depends on SCMI_FIRMWARE
164 help
165 Enable this option if you want to support clock devices exposed
166 by a SCMI agent based on SCMI clock protocol communication
167 with a SCMI server.
168
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +0300169config CLK_HSDK
Eugeniy Paltsev6bd63fc2020-05-07 22:20:10 +0300170 bool "Enable cgu clock driver for HSDK boards"
171 depends on CLK && TARGET_HSDK
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +0300172 help
Eugeniy Paltsev6bd63fc2020-05-07 22:20:10 +0300173 Enable this to support the cgu clocks on Synopsys ARC HSDK and
174 Synopsys ARC HSDK-4xD boards
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +0300175
Sean Andersond1f48b52021-12-15 11:36:19 -0500176config CLK_VERSACLOCK
177 tristate "Enable VersaClock 5/6 devices"
178 depends on CLK
179 depends on CLK_CCF
180 depends on OF_CONTROL
181 help
182 This driver supports the IDT VersaClock 5 and VersaClock 6
183 programmable clock generators.
184
Siva Durga Prasad Paladuguf7a71202019-06-23 12:24:57 +0530185config CLK_VERSAL
186 bool "Enable clock driver support for Versal"
187 depends on ARCH_VERSAL
188 select ZYNQMP_FIRMWARE
189 help
190 This clock driver adds support for clock realted settings for
191 Versal platform.
192
Liviu Dudauba024e62018-09-17 17:50:00 +0100193config CLK_VEXPRESS_OSC
194 bool "Enable driver for Arm Versatile Express OSC clock generators"
195 depends on CLK && VEXPRESS_CONFIG
196 help
197 This clock driver adds support for clock generators present on
198 Arm Versatile Express platforms.
199
Zhengxun39df0532021-06-11 15:10:48 +0000200config CLK_XLNX_CLKWZRD
201 bool "Xilinx Clocking Wizard"
202 depends on CLK
203 help
204 Support for the Xilinx Clocking Wizard IP core clock generator.
205 The wizard support for dynamically reconfiguring the clocking
206 primitives for Multiply, Divide, Phase Shift/Offset, or Duty
207 Cycle. Limited by U-Boot clk uclass without set_phase API and
208 set_duty_cycle API, this driver only supports set_rate to modify
209 the frequency.
210
Sean Andersond1f48b52021-12-15 11:36:19 -0500211config CLK_ZYNQ
212 bool "Enable clock driver support for Zynq"
213 depends on CLK && ARCH_ZYNQ
214 default y
215 help
216 This clock driver adds support for clock related settings for
217 Zynq platform.
218
Siva Durga Prasad Paladugu468b55f2016-11-15 16:15:41 +0530219config CLK_ZYNQMP
220 bool "Enable clock driver support for ZynqMP"
221 depends on ARCH_ZYNQMP
Rajan Vaja833be322019-02-15 04:45:32 -0800222 select ZYNQMP_FIRMWARE
Siva Durga Prasad Paladugu468b55f2016-11-15 16:15:41 +0530223 help
224 This clock driver adds support for clock realted settings for
225 ZynqMP platform.
226
Anup Patel00a156d2019-06-25 06:31:02 +0000227source "drivers/clk/analogbits/Kconfig"
Wenyou Yang8c772bd2016-07-20 17:55:12 +0800228source "drivers/clk/at91/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530229source "drivers/clk/exynos/Kconfig"
Peng Fan5e80d5a2018-10-18 14:28:30 +0200230source "drivers/clk/imx/Kconfig"
Jerome Brunet3da39a82019-02-10 14:54:30 +0100231source "drivers/clk/meson/Kconfig"
Padmarao Begari0c4ae802021-01-15 08:20:38 +0530232source "drivers/clk/microchip/Kconfig"
Marek BehĂșn61d74e82018-04-24 17:21:25 +0200233source "drivers/clk/mvebu/Kconfig"
Manivannan Sadhasivam91a85132018-06-14 23:38:35 +0530234source "drivers/clk/owl/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530235source "drivers/clk/renesas/Kconfig"
Jagan Teki1d150b42018-12-22 21:32:49 +0530236source "drivers/clk/sunxi/Kconfig"
Anup Patel42fdf082019-02-25 08:14:49 +0000237source "drivers/clk/sifive/Kconfig"
Patrick Delaunay12427612022-05-19 17:56:45 +0200238source "drivers/clk/stm32/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530239source "drivers/clk/tegra/Kconfig"
Dario Binacchida3b0202020-12-30 00:06:32 +0100240source "drivers/clk/ti/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530241source "drivers/clk/uniphier/Kconfig"
Masahiro Yamadae4dfb052016-02-02 21:11:32 +0900242
Masahiro Yamada92b8c2f2016-01-12 16:36:38 +0900243endmenu