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git01.mediatek.com / filogic / uboot / 8e738cef46bda204774004678a53beb14a79625b / . / arch / m68k / include / asm / immap.h
blob: f0a76f43778914f233bcdb6f9a03df2d05136b13 [file] [log] [blame]
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]1/*
2 * ColdFire Internal Memory Map and Defines
3 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]4 * Copyright 2004-2012 Freescale Semiconductor, Inc.
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]8 */
9
10#ifndef __IMMAP_H
11#define __IMMAP_H
Stefan Roesef1110122007-07-16 13:11:12 +0200[diff] [blame]12
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]13#if defined(CONFIG_MCF520x)
14#include <asm/immap_520x.h>
15#include <asm/m520x.h>
16
17#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
18#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
19
20/* Timer */
21#ifdef CONFIG_MCFTMR
22#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
23#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
24#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
25#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
26#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
27#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
28#define CONFIG_SYS_TMRINTR_PRI (6)
29#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
30#endif
31
32#ifdef CONFIG_MCFPIT
33#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
34#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
35#define CONFIG_SYS_PIT_PRESCALE (6)
36#endif
37
38#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
39#define CONFIG_SYS_NUM_IRQS (128)
40#endif /* CONFIG_M520x */
41
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]42#ifdef CONFIG_M52277
43#include <asm/immap_5227x.h>
44#include <asm/m5227x.h>
45
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]46#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]47
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]48#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]49
50#ifdef CONFIG_LCD
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]51#define CONFIG_SYS_LCD_BASE (MMAP_LCD)
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]52#endif
53
54/* Timer */
55#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]56#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
57#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
58#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
59#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
60#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
61#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
62#define CONFIG_SYS_TMRINTR_PRI (6)
63#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]64#endif
65
66#ifdef CONFIG_MCFPIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]67#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
68#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
69#define CONFIG_SYS_PIT_PRESCALE (6)
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]70#endif
71
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]72#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
73#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]74#endif /* CONFIG_M52277 */
75
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]76#ifdef CONFIG_M5235
77#include <asm/immap_5235.h>
78#include <asm/m5235.h>
79
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]80#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
81#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]82
83/* Timer */
84#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]85#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
86#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
87#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
88#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
89#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
90#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
91#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
92#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]93#endif
94
95#ifdef CONFIG_MCFPIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]96#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
97#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
98#define CONFIG_SYS_PIT_PRESCALE (6)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]99#endif
100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]101#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
102#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]103#endif /* CONFIG_M5235 */
104
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]105#ifdef CONFIG_M5249
106#include <asm/immap_5249.h>
107#include <asm/m5249.h>
108
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]109#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]110
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]111#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
112#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]113
114/* Timer */
115#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]116#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
117#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
118#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
119#define CONFIG_SYS_TMRINTR_NO (31)
120#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
121#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
122#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
123#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]124#endif
125#endif /* CONFIG_M5249 */
126
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]127#ifdef CONFIG_M5253
128#include <asm/immap_5253.h>
129#include <asm/m5249.h>
130#include <asm/m5253.h>
131
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]132#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]133
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]134#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
135#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]136
137/* Timer */
138#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]139#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
140#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
141#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
142#define CONFIG_SYS_TMRINTR_NO (27)
143#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
144#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
145#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
146#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]147#endif
148#endif /* CONFIG_M5253 */
149
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]150#ifdef CONFIG_M5271
151#include <asm/immap_5271.h>
152#include <asm/m5271.h>
153
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]154#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
155#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]156
157/* Timer */
158#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]159#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
160#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
161#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
162#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
163#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
164#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
Richard Retanubun0dd94312009-03-26 15:26:01 -0400[diff] [blame]165#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]166#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]167#endif
168
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]169#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
170#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]171#endif /* CONFIG_M5271 */
172
173#ifdef CONFIG_M5272
174#include <asm/immap_5272.h>
175#include <asm/m5272.h>
176
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]177#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
178#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]179
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]180#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
181#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]182
183/* Timer */
184#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]185#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
186#define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
187#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
188#define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
189#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
190#define CONFIG_SYS_TMRINTR_PEND (0)
191#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
192#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]193#endif
194#endif /* CONFIG_M5272 */
195
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]196#ifdef CONFIG_M5275
197#include <asm/immap_5275.h>
198#include <asm/m5275.h>
199
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]200#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
201#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
202#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]203
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]204#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
205#define CONFIG_SYS_NUM_IRQS (192)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]206
207/* Timer */
208#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]209#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
210#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
211#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
212#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
213#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
214#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
215#define CONFIG_SYS_TMRINTR_PRI (0x1E)
216#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]217#endif
218#endif /* CONFIG_M5275 */
219
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]220#ifdef CONFIG_M5282
221#include <asm/immap_5282.h>
222#include <asm/m5282.h>
223
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]224#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
225#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]226
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]227#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
228#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]229
230/* Timer */
231#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]232#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
233#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
234#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
235#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
236#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
237#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
238#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
239#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]240#endif
241#endif /* CONFIG_M5282 */
242
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]243#if defined(CONFIG_MCF5301x)
244#include <asm/immap_5301x.h>
245#include <asm/m5301x.h>
246
247#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
248#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
249#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
250
251#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
252
253/* Timer */
254#ifdef CONFIG_MCFTMR
255#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
256#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
257#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
258#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
259#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
260#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
261#define CONFIG_SYS_TMRINTR_PRI (6)
262#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
263#endif
264
265#ifdef CONFIG_MCFPIT
266#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
267#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
268#define CONFIG_SYS_PIT_PRESCALE (6)
269#endif
270
271#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
272#define CONFIG_SYS_NUM_IRQS (128)
273#endif /* CONFIG_M5301x */
274
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600[diff] [blame]275#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]276#include <asm/immap_5329.h>
277#include <asm/m5329.h>
278
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]279#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
280#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
281#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]282
283/* Timer */
284#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]285#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
286#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
287#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
288#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
289#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
290#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
291#define CONFIG_SYS_TMRINTR_PRI (6)
292#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]293#endif
294
295#ifdef CONFIG_MCFPIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]296#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
297#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
298#define CONFIG_SYS_PIT_PRESCALE (6)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]299#endif
300
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]301#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
302#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600[diff] [blame]303#endif /* CONFIG_M5329 && CONFIG_M5373 */
Stefan Roesef1110122007-07-16 13:11:12 +0200[diff] [blame]304
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]305#if defined(CONFIG_M54418)
306#include <asm/immap_5441x.h>
307#include <asm/m5441x.h>
308
309#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
310#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
311
312#if (CONFIG_SYS_UART_PORT < 4)
313#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
314 (CONFIG_SYS_UART_PORT * 0x4000))
315#else
316#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
317 ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
318#endif
319
320#define MMAP_DSPI MMAP_DSPI0
321#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
322
323/* Timer */
324#ifdef CONFIG_MCFTMR
325#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
326#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
327#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
328#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
329#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
330#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
331#define CONFIG_SYS_TMRINTR_PRI (6)
332#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
333#endif
334
335#ifdef CONFIG_MCFPIT
336#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
337#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
338#define CONFIG_SYS_PIT_PRESCALE (6)
339#endif
340
341#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
342#define CONFIG_SYS_NUM_IRQS (128)
343
344#endif /* CONFIG_M54418 */
345
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000[diff] [blame]346#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]347#include <asm/immap_5445x.h>
348#include <asm/m5445x.h>
349
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]350#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000[diff] [blame]351#if defined(CONFIG_M54455EVB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]352#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000[diff] [blame]353#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]354
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]355#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]356
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]357#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]358
359/* Timer */
360#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]361#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
362#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
363#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
364#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
365#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
366#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
367#define CONFIG_SYS_TMRINTR_PRI (6)
368#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]369#endif
370
371#ifdef CONFIG_MCFPIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]372#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
373#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
374#define CONFIG_SYS_PIT_PRESCALE (6)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]375#endif
376
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]377#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
378#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]379
380#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]381#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
382#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE)
383#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
384#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]385#endif
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000[diff] [blame]386#endif /* CONFIG_M54451 || CONFIG_M54455 */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]387
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]388#ifdef CONFIG_M547x
389#include <asm/immap_547x_8x.h>
390#include <asm/m547x_8x.h>
391
392#ifdef CONFIG_FSLDMAFEC
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]393#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
394#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]395
396#define FEC0_RX_TASK 0
397#define FEC0_TX_TASK 1
398#define FEC0_RX_PRIORITY 6
399#define FEC0_TX_PRIORITY 7
400#define FEC0_RX_INIT 16
401#define FEC0_TX_INIT 17
402#define FEC1_RX_TASK 2
403#define FEC1_TX_TASK 3
404#define FEC1_RX_PRIORITY 6
405#define FEC1_TX_PRIORITY 7
406#define FEC1_RX_INIT 30
407#define FEC1_TX_INIT 31
408#endif
409
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]410#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]411
412#ifdef CONFIG_SLTTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]413#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
414#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
415#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
416#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
417#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
418#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
419#define CONFIG_SYS_TMRINTR_PRI (0x1E)
420#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]421#endif
422
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]423#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
424#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]425
426#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]427#define CONFIG_SYS_PCI_BAR0 (0x40000000)
428#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
429#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
430#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]431#endif
432#endif /* CONFIG_M547x */
433
434#ifdef CONFIG_M548x
435#include <asm/immap_547x_8x.h>
436#include <asm/m547x_8x.h>
437
438#ifdef CONFIG_FSLDMAFEC
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]439#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
440#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]441
442#define FEC0_RX_TASK 0
443#define FEC0_TX_TASK 1
444#define FEC0_RX_PRIORITY 6
445#define FEC0_TX_PRIORITY 7
446#define FEC0_RX_INIT 16
447#define FEC0_TX_INIT 17
448#define FEC1_RX_TASK 2
449#define FEC1_TX_TASK 3
450#define FEC1_RX_PRIORITY 6
451#define FEC1_TX_PRIORITY 7
452#define FEC1_RX_INIT 30
453#define FEC1_TX_INIT 31
454#endif
455
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]456#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]457
458/* Timer */
459#ifdef CONFIG_SLTTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]460#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
461#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
462#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
463#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
464#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
465#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
466#define CONFIG_SYS_TMRINTR_PRI (0x1E)
467#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]468#endif
469
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]470#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
471#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]472
473#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]474#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
475#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
476#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
477#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]478#endif
479#endif /* CONFIG_M548x */
480
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]481#endif /* __IMMAP_H */