Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | #include <dt-bindings/input/input.h> |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 4 | #include "tegra30.dtsi" |
| 5 | |
| 6 | / { |
| 7 | chosen { |
| 8 | stdout-path = &uarta; |
| 9 | }; |
| 10 | |
| 11 | aliases { |
| 12 | i2c0 = &pwr_i2c; |
| 13 | i2c1 = &gen1_i2c; |
| 14 | |
| 15 | mmc0 = &sdmmc4; /* eMMC */ |
| 16 | mmc1 = &sdmmc1; /* uSD slot */ |
| 17 | |
| 18 | rtc0 = &pmic; |
| 19 | rtc1 = "/rtc@7000e000"; |
| 20 | |
| 21 | usb0 = &usb1; |
| 22 | usb1 = &usb3; /* Dock USB */ |
| 23 | }; |
| 24 | |
| 25 | memory { |
| 26 | device_type = "memory"; |
| 27 | reg = <0x80000000 0x40000000>; |
| 28 | }; |
| 29 | |
| 30 | host1x@50000000 { |
| 31 | dc@54200000 { |
| 32 | rgb { |
| 33 | status = "okay"; |
| 34 | |
| 35 | nvidia,panel = <&panel>; |
| 36 | }; |
| 37 | }; |
| 38 | }; |
| 39 | |
Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 40 | pinmux@70000868 { |
| 41 | pinctrl-names = "default"; |
| 42 | pinctrl-0 = <&state_default>; |
| 43 | |
| 44 | state_default: pinmux { |
| 45 | /* SDMMC1 pinmux */ |
| 46 | sdmmc1_clk { |
| 47 | nvidia,pins = "sdmmc1_clk_pz0"; |
| 48 | nvidia,function = "sdmmc1"; |
| 49 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 50 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 51 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 52 | }; |
| 53 | |
| 54 | sdmmc1_cmd { |
| 55 | nvidia,pins = "sdmmc1_dat3_py4", |
| 56 | "sdmmc1_dat2_py5", |
| 57 | "sdmmc1_dat1_py6", |
| 58 | "sdmmc1_dat0_py7", |
| 59 | "sdmmc1_cmd_pz1"; |
| 60 | nvidia,function = "sdmmc1"; |
| 61 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 62 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 63 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 64 | }; |
| 65 | |
| 66 | sdmmc1_cd { |
| 67 | nvidia,pins = "gmi_iordy_pi5"; |
| 68 | nvidia,function = "rsvd1"; |
| 69 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 70 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 71 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 72 | }; |
| 73 | |
| 74 | sdmmc1_wp { |
| 75 | nvidia,pins = "vi_d11_pt3"; |
| 76 | nvidia,function = "rsvd2"; |
| 77 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 78 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 79 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 80 | }; |
| 81 | |
| 82 | /* SDMMC2 pinmux */ |
| 83 | vi_d1_pd5 { |
| 84 | nvidia,pins = "vi_d1_pd5", |
| 85 | "vi_d2_pl0", |
| 86 | "vi_d3_pl1", |
| 87 | "vi_d5_pl3", |
| 88 | "vi_d7_pl5"; |
| 89 | nvidia,function = "sdmmc2"; |
| 90 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 91 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 92 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 93 | }; |
| 94 | |
| 95 | vi_d8_pl6 { |
| 96 | nvidia,pins = "vi_d8_pl6", |
| 97 | "vi_d9_pl7"; |
| 98 | nvidia,function = "sdmmc2"; |
| 99 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 100 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 101 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Svyatoslav Ryhel | cc81ef9 | 2024-01-20 15:06:23 +0200 | [diff] [blame] | 102 | nvidia,lock = <1>; |
| 103 | nvidia,io-reset = <1>; |
Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 104 | }; |
| 105 | |
| 106 | /* SDMMC3 pinmux */ |
| 107 | sdmmc3_clk { |
| 108 | nvidia,pins = "sdmmc3_clk_pa6"; |
| 109 | nvidia,function = "sdmmc3"; |
| 110 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 111 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 112 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 113 | }; |
| 114 | |
| 115 | sdmmc3_cmd { |
| 116 | nvidia,pins = "sdmmc3_cmd_pa7", |
| 117 | "sdmmc3_dat0_pb7", |
| 118 | "sdmmc3_dat1_pb6", |
| 119 | "sdmmc3_dat2_pb5", |
| 120 | "sdmmc3_dat3_pb4", |
| 121 | "sdmmc3_dat4_pd1", |
| 122 | "sdmmc3_dat5_pd0", |
| 123 | "sdmmc3_dat6_pd3", |
| 124 | "sdmmc3_dat7_pd4"; |
| 125 | nvidia,function = "sdmmc3"; |
| 126 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 127 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 128 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 129 | }; |
| 130 | |
| 131 | /* SDMMC4 pinmux */ |
| 132 | sdmmc4_clk { |
| 133 | nvidia,pins = "sdmmc4_clk_pcc4"; |
| 134 | nvidia,function = "sdmmc4"; |
| 135 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 136 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 137 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 138 | }; |
| 139 | |
| 140 | sdmmc4_cmd { |
| 141 | nvidia,pins = "sdmmc4_cmd_pt7", |
| 142 | "sdmmc4_dat0_paa0", |
| 143 | "sdmmc4_dat1_paa1", |
| 144 | "sdmmc4_dat2_paa2", |
| 145 | "sdmmc4_dat3_paa3", |
| 146 | "sdmmc4_dat4_paa4", |
| 147 | "sdmmc4_dat5_paa5", |
| 148 | "sdmmc4_dat6_paa6", |
| 149 | "sdmmc4_dat7_paa7"; |
| 150 | nvidia,function = "sdmmc4"; |
| 151 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 152 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 153 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 154 | }; |
| 155 | |
| 156 | sdmmc4_rst_n { |
| 157 | nvidia,pins = "sdmmc4_rst_n_pcc3"; |
| 158 | nvidia,function = "rsvd2"; |
| 159 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 160 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 161 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 162 | }; |
| 163 | |
| 164 | cam_mclk { |
| 165 | nvidia,pins = "cam_mclk_pcc0"; |
| 166 | nvidia,function = "vi_alt3"; |
| 167 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 169 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 170 | }; |
| 171 | |
| 172 | drive_sdmmc4 { |
| 173 | nvidia,pins = "drive_gma", |
| 174 | "drive_gmb", |
| 175 | "drive_gmc", |
| 176 | "drive_gmd"; |
| 177 | nvidia,pull-down-strength = <9>; |
| 178 | nvidia,pull-up-strength = <9>; |
| 179 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 180 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 181 | }; |
| 182 | |
| 183 | /* I2C pinmux */ |
| 184 | gen1_i2c { |
| 185 | nvidia,pins = "gen1_i2c_scl_pc4", |
| 186 | "gen1_i2c_sda_pc5"; |
| 187 | nvidia,function = "i2c1"; |
| 188 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 190 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 191 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
Svyatoslav Ryhel | cc81ef9 | 2024-01-20 15:06:23 +0200 | [diff] [blame] | 192 | nvidia,lock = <1>; |
Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 193 | }; |
| 194 | |
| 195 | gen2_i2c { |
| 196 | nvidia,pins = "gen2_i2c_scl_pt5", |
| 197 | "gen2_i2c_sda_pt6"; |
| 198 | nvidia,function = "i2c2"; |
| 199 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 200 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 201 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 202 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
Svyatoslav Ryhel | cc81ef9 | 2024-01-20 15:06:23 +0200 | [diff] [blame] | 203 | nvidia,lock = <1>; |
Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 204 | }; |
| 205 | |
| 206 | cam_i2c { |
| 207 | nvidia,pins = "cam_i2c_scl_pbb1", |
| 208 | "cam_i2c_sda_pbb2"; |
| 209 | nvidia,function = "i2c3"; |
| 210 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 211 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 212 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 213 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
Svyatoslav Ryhel | cc81ef9 | 2024-01-20 15:06:23 +0200 | [diff] [blame] | 214 | nvidia,lock = <1>; |
Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 215 | }; |
| 216 | |
| 217 | ddc_i2c { |
| 218 | nvidia,pins = "ddc_scl_pv4", |
| 219 | "ddc_sda_pv5"; |
| 220 | nvidia,function = "i2c4"; |
| 221 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 222 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 223 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Svyatoslav Ryhel | cc81ef9 | 2024-01-20 15:06:23 +0200 | [diff] [blame] | 224 | nvidia,lock = <1>; |
Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 225 | }; |
| 226 | |
| 227 | pwr_i2c { |
| 228 | nvidia,pins = "pwr_i2c_scl_pz6", |
| 229 | "pwr_i2c_sda_pz7"; |
| 230 | nvidia,function = "i2cpwr"; |
| 231 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 232 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 233 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 234 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
Svyatoslav Ryhel | cc81ef9 | 2024-01-20 15:06:23 +0200 | [diff] [blame] | 235 | nvidia,lock = <1>; |
Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 236 | }; |
| 237 | |
| 238 | hotplug_i2c { |
| 239 | nvidia,pins = "pu4"; |
| 240 | nvidia,function = "rsvd4"; |
| 241 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 242 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 243 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 244 | }; |
| 245 | |
| 246 | /* HDMI pinmux */ |
| 247 | hdmi_cec { |
| 248 | nvidia,pins = "hdmi_cec_pee3"; |
| 249 | nvidia,function = "cec"; |
| 250 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 251 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 252 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 253 | }; |
| 254 | |
| 255 | hdmi_hpd { |
| 256 | nvidia,pins = "hdmi_int_pn7"; |
| 257 | nvidia,function = "hdmi"; |
| 258 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 259 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 260 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 261 | }; |
| 262 | |
| 263 | /* UART-A */ |
| 264 | ulpi_data0_po1 { |
| 265 | nvidia,pins = "ulpi_data0_po1"; |
| 266 | nvidia,function = "uarta"; |
| 267 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 268 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 269 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 270 | }; |
| 271 | |
| 272 | ulpi_data1_po2 { |
| 273 | nvidia,pins = "ulpi_data1_po2"; |
| 274 | nvidia,function = "uarta"; |
| 275 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 276 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 277 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 278 | }; |
| 279 | |
| 280 | ulpi_data5_po6 { |
| 281 | nvidia,pins = "ulpi_data5_po6"; |
| 282 | nvidia,function = "uarta"; |
| 283 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 284 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 285 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 286 | }; |
| 287 | |
| 288 | ulpi_data7_po0 { |
| 289 | nvidia,pins = "ulpi_data7_po0", |
| 290 | "ulpi_data2_po3", |
| 291 | "ulpi_data3_po4", |
| 292 | "ulpi_data4_po5", |
| 293 | "ulpi_data6_po7"; |
| 294 | nvidia,function = "uarta"; |
| 295 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 296 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 297 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 298 | }; |
| 299 | |
| 300 | /* UART-B */ |
| 301 | uartb_txd_rts { |
| 302 | nvidia,pins = "uart2_txd_pc2", |
| 303 | "uart2_rts_n_pj6"; |
| 304 | nvidia,function = "uartb"; |
| 305 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 306 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 307 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 308 | }; |
| 309 | |
| 310 | uartb_rxd_cts { |
| 311 | nvidia,pins = "uart2_rxd_pc3", |
| 312 | "uart2_cts_n_pj5"; |
| 313 | nvidia,function = "uartb"; |
| 314 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 315 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 316 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 317 | }; |
| 318 | |
| 319 | /* UART-C */ |
| 320 | uartc_rxd_cts { |
| 321 | nvidia,pins = "uart3_cts_n_pa1", |
| 322 | "uart3_rxd_pw7"; |
| 323 | nvidia,function = "uartc"; |
| 324 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 325 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 326 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 327 | }; |
| 328 | |
| 329 | uartc_txd_rts { |
| 330 | nvidia,pins = "uart3_rts_n_pc0", |
| 331 | "uart3_txd_pw6"; |
| 332 | nvidia,function = "uartc"; |
| 333 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 334 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 335 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 336 | }; |
| 337 | |
| 338 | /* UART-D */ |
| 339 | ulpi_nxt_py2 { |
| 340 | nvidia,pins = "ulpi_nxt_py2"; |
| 341 | nvidia,function = "uartd"; |
| 342 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 343 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 344 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 345 | }; |
| 346 | |
| 347 | ulpi_clk_py0 { |
| 348 | nvidia,pins = "ulpi_clk_py0", |
| 349 | "ulpi_dir_py1", |
| 350 | "ulpi_stp_py3"; |
| 351 | nvidia,function = "uartd"; |
| 352 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 353 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 354 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 355 | }; |
| 356 | |
| 357 | /* I2S pinmux */ |
| 358 | dap_i2s0 { |
| 359 | nvidia,pins = "dap1_fs_pn0", |
| 360 | "dap1_din_pn1", |
| 361 | "dap1_dout_pn2", |
| 362 | "dap1_sclk_pn3"; |
| 363 | nvidia,function = "i2s0"; |
| 364 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 365 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 366 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 367 | }; |
| 368 | |
| 369 | dap_i2s1 { |
| 370 | nvidia,pins = "dap2_fs_pa2", |
| 371 | "dap2_sclk_pa3", |
| 372 | "dap2_din_pa4", |
| 373 | "dap2_dout_pa5"; |
| 374 | nvidia,function = "i2s1"; |
| 375 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 376 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 377 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 378 | }; |
| 379 | |
| 380 | dap3_fs { |
| 381 | nvidia,pins = "dap3_fs_pp0", |
| 382 | "dap3_din_pp1"; |
| 383 | nvidia,function = "i2s2"; |
| 384 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 385 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 386 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 387 | }; |
| 388 | |
| 389 | dap3_dout { |
| 390 | nvidia,pins = "dap3_dout_pp2", |
| 391 | "dap3_sclk_pp3"; |
| 392 | nvidia,function = "i2s2"; |
| 393 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 394 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 395 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 396 | }; |
| 397 | |
| 398 | dap_i2s3 { |
| 399 | nvidia,pins = "dap4_fs_pp4", |
| 400 | "dap4_din_pp5", |
| 401 | "dap4_dout_pp6", |
| 402 | "dap4_sclk_pp7"; |
| 403 | nvidia,function = "i2s3"; |
| 404 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 405 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 406 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 407 | }; |
| 408 | |
| 409 | /* Sensors pinmux */ |
| 410 | nct_irq { |
| 411 | nvidia,pins = "pcc2"; |
| 412 | nvidia,function = "i2s4"; |
| 413 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 414 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 415 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 416 | }; |
| 417 | |
| 418 | /* Asus EC pinmux */ |
| 419 | ec_irqs { |
| 420 | nvidia,pins = "kb_row10_ps2", |
| 421 | "kb_row15_ps7"; |
| 422 | nvidia,function = "kbc"; |
| 423 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 424 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 425 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 426 | }; |
| 427 | |
| 428 | ec_reqs { |
| 429 | nvidia,pins = "kb_col1_pq1"; |
| 430 | nvidia,function = "kbc"; |
| 431 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 432 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 433 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 434 | }; |
| 435 | |
| 436 | /* Memory type bootstrap */ |
| 437 | mem_boostraps { |
| 438 | nvidia,pins = "gmi_ad4_pg4", |
| 439 | "gmi_ad5_pg5"; |
| 440 | nvidia,function = "nand"; |
| 441 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 442 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 443 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 444 | }; |
| 445 | |
| 446 | /* PCI-e pinmux */ |
| 447 | pex_l2_rst_n { |
| 448 | nvidia,pins = "pex_l2_rst_n_pcc6", |
| 449 | "pex_l0_rst_n_pdd1", |
| 450 | "pex_l1_rst_n_pdd5"; |
| 451 | nvidia,function = "pcie"; |
| 452 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 453 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 454 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 455 | }; |
| 456 | |
| 457 | pex_l2_clkreq_n { |
| 458 | nvidia,pins = "pex_l2_clkreq_n_pcc7", |
| 459 | "pex_l0_prsnt_n_pdd0", |
| 460 | "pex_l0_clkreq_n_pdd2", |
| 461 | "pex_wake_n_pdd3", |
| 462 | "pex_l1_prsnt_n_pdd4", |
| 463 | "pex_l1_clkreq_n_pdd6", |
| 464 | "pex_l2_prsnt_n_pdd7"; |
| 465 | nvidia,function = "pcie"; |
| 466 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 467 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 468 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 469 | }; |
| 470 | |
| 471 | /* SPI pinmux */ |
| 472 | spi1_mosi_px4 { |
| 473 | nvidia,pins = "spi1_mosi_px4", |
| 474 | "spi1_sck_px5", |
| 475 | "spi1_cs0_n_px6", |
| 476 | "spi1_miso_px7"; |
| 477 | nvidia,function = "spi1"; |
| 478 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 479 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 480 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 481 | }; |
| 482 | |
| 483 | hp_detect { |
| 484 | nvidia,pins = "spi2_cs1_n_pw2"; |
| 485 | nvidia,function = "spi2"; |
| 486 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 487 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 488 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 489 | }; |
| 490 | |
| 491 | mic_detect { |
| 492 | nvidia,pins = "spi2_sck_px2"; |
| 493 | nvidia,function = "spi2"; |
| 494 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 495 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 496 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 497 | }; |
| 498 | |
| 499 | gmi_a17_pb0 { |
| 500 | nvidia,pins = "gmi_a17_pb0", |
| 501 | "gmi_a16_pj7"; |
| 502 | nvidia,function = "spi4"; |
| 503 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 504 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 505 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 506 | }; |
| 507 | |
| 508 | gmi_a18_pb1 { |
| 509 | nvidia,pins = "gmi_a18_pb1"; |
| 510 | nvidia,function = "spi4"; |
| 511 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 512 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 513 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 514 | }; |
| 515 | |
| 516 | gmi_a19_pk7 { |
| 517 | nvidia,pins = "gmi_a19_pk7"; |
| 518 | nvidia,function = "spi4"; |
| 519 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 520 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 521 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 522 | }; |
| 523 | |
| 524 | /* Display A pinmux */ |
| 525 | lcd_pwr0_pb2 { |
| 526 | nvidia,pins = "lcd_pwr0_pb2", |
| 527 | "lcd_pclk_pb3", |
| 528 | "lcd_pwr1_pc1", |
| 529 | "lcd_d0_pe0", |
| 530 | "lcd_d1_pe1", |
| 531 | "lcd_d2_pe2", |
| 532 | "lcd_d3_pe3", |
| 533 | "lcd_d4_pe4", |
| 534 | "lcd_d5_pe5", |
| 535 | "lcd_d6_pe6", |
| 536 | "lcd_d7_pe7", |
| 537 | "lcd_d8_pf0", |
| 538 | "lcd_d9_pf1", |
| 539 | "lcd_d10_pf2", |
| 540 | "lcd_d11_pf3", |
| 541 | "lcd_d12_pf4", |
| 542 | "lcd_d13_pf5", |
| 543 | "lcd_d14_pf6", |
| 544 | "lcd_d15_pf7", |
| 545 | "lcd_de_pj1", |
| 546 | "lcd_hsync_pj3", |
| 547 | "lcd_vsync_pj4", |
| 548 | "lcd_d16_pm0", |
| 549 | "lcd_d17_pm1", |
| 550 | "lcd_d18_pm2", |
| 551 | "lcd_d19_pm3", |
| 552 | "lcd_d20_pm4", |
| 553 | "lcd_d21_pm5", |
| 554 | "lcd_d22_pm6", |
| 555 | "lcd_d23_pm7", |
| 556 | "lcd_cs1_n_pw0", |
| 557 | "lcd_m1_pw1", |
| 558 | "lcd_dc0_pn6", |
| 559 | "lcd_sck_pz4", |
| 560 | "lcd_sdin_pz2"; |
| 561 | nvidia,function = "displaya"; |
| 562 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 563 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 564 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 565 | }; |
| 566 | |
| 567 | lcd_cs0_n_pn4 { |
| 568 | nvidia,pins = "lcd_cs0_n_pn4", |
| 569 | "lcd_sdout_pn5", |
| 570 | "lcd_wr_n_pz3"; |
| 571 | nvidia,function = "displaya"; |
| 572 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 573 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 574 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 575 | }; |
| 576 | |
| 577 | blink { |
| 578 | nvidia,pins = "clk_32k_out_pa0"; |
| 579 | nvidia,function = "blink"; |
| 580 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 581 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 582 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 583 | }; |
| 584 | |
| 585 | /* KBC keys */ |
| 586 | kb_col0_pq0 { |
| 587 | nvidia,pins = "kb_col0_pq0"; |
| 588 | nvidia,function = "kbc"; |
| 589 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 590 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 591 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 592 | }; |
| 593 | |
| 594 | kb_col1_pq1 { |
| 595 | nvidia,pins = "kb_row1_pr1", |
| 596 | "kb_row3_pr3", |
| 597 | "kb_row6_pr6", |
| 598 | "kb_row8_ps0", |
| 599 | "kb_row9_ps1", |
| 600 | "kb_row11_ps3", |
| 601 | "kb_row14_ps6", |
| 602 | "kb_col6_pq6"; |
| 603 | nvidia,function = "kbc"; |
| 604 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 605 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 606 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 607 | }; |
| 608 | |
| 609 | kb_col4_pq4 { |
| 610 | nvidia,pins = "kb_col4_pq4", |
| 611 | "kb_col5_pq5", |
| 612 | "kb_col7_pq7", |
| 613 | "kb_row2_pr2", |
| 614 | "kb_row4_pr4", |
| 615 | "kb_row5_pr5", |
| 616 | "kb_row12_ps4", |
| 617 | "kb_row13_ps5"; |
| 618 | nvidia,function = "kbc"; |
| 619 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 620 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 621 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 622 | }; |
| 623 | |
| 624 | gmi_wp_n_pc7 { |
| 625 | nvidia,pins = "gmi_wp_n_pc7", |
| 626 | "gmi_wait_pi7", |
| 627 | "gmi_cs3_n_pk4"; |
| 628 | nvidia,function = "rsvd1"; |
| 629 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 630 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 631 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 632 | }; |
| 633 | |
| 634 | gmi_cs0_n_pj0 { |
| 635 | nvidia,pins = "gmi_cs0_n_pj0", |
| 636 | "gmi_cs1_n_pj2", |
| 637 | "gmi_cs2_n_pk3"; |
| 638 | nvidia,function = "rsvd1"; |
| 639 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 640 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 641 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 642 | }; |
| 643 | |
| 644 | vi_pclk_pt0 { |
| 645 | nvidia,pins = "vi_pclk_pt0"; |
| 646 | nvidia,function = "rsvd1"; |
| 647 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 648 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 649 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Svyatoslav Ryhel | cc81ef9 | 2024-01-20 15:06:23 +0200 | [diff] [blame] | 650 | nvidia,lock = <1>; |
| 651 | nvidia,io-reset = <1>; |
Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 652 | }; |
| 653 | |
| 654 | /* GPIO keys pinmux */ |
| 655 | power_key { |
| 656 | nvidia,pins = "pv0"; |
| 657 | nvidia,function = "rsvd1"; |
| 658 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 659 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 660 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 661 | }; |
| 662 | |
| 663 | vol_keys { |
| 664 | nvidia,pins = "kb_col2_pq2", |
| 665 | "kb_col3_pq3"; |
| 666 | nvidia,function = "rsvd4"; |
| 667 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 668 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 669 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 670 | }; |
| 671 | |
| 672 | /* Bluetooth */ |
| 673 | bt_shutdown { |
| 674 | nvidia,pins = "pu0"; |
| 675 | nvidia,function = "rsvd4"; |
| 676 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 677 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 678 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 679 | }; |
| 680 | |
| 681 | bt_dev_wake { |
| 682 | nvidia,pins = "pu1"; |
| 683 | nvidia,function = "rsvd1"; |
| 684 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 685 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 686 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 687 | }; |
| 688 | |
| 689 | bt_host_wake { |
| 690 | nvidia,pins = "pu6"; |
| 691 | nvidia,function = "rsvd4"; |
| 692 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 693 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 694 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 695 | }; |
| 696 | |
| 697 | pu2 { |
| 698 | nvidia,pins = "pu2"; |
| 699 | nvidia,function = "rsvd1"; |
| 700 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 701 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 702 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 703 | }; |
| 704 | |
| 705 | pu3 { |
| 706 | nvidia,pins = "pu3"; |
| 707 | nvidia,function = "rsvd4"; |
| 708 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 709 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 710 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 711 | }; |
| 712 | |
| 713 | pcc1 { |
| 714 | nvidia,pins = "pcc1"; |
| 715 | nvidia,function = "rsvd2"; |
| 716 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 717 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 718 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 719 | }; |
| 720 | |
| 721 | pv2 { |
| 722 | nvidia,pins = "pv2"; |
| 723 | nvidia,function = "rsvd2"; |
| 724 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 725 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 726 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 727 | }; |
| 728 | |
| 729 | pv3 { |
| 730 | nvidia,pins = "pv3"; |
| 731 | nvidia,function = "rsvd2"; |
| 732 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 733 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 734 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 735 | }; |
| 736 | |
| 737 | vi_vsync_pd6 { |
| 738 | nvidia,pins = "vi_vsync_pd6", |
| 739 | "vi_hsync_pd7"; |
| 740 | nvidia,function = "rsvd2"; |
| 741 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 742 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 743 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Svyatoslav Ryhel | cc81ef9 | 2024-01-20 15:06:23 +0200 | [diff] [blame] | 744 | nvidia,lock = <1>; |
| 745 | nvidia,io-reset = <1>; |
Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 746 | }; |
| 747 | |
| 748 | vi_d10_pt2 { |
| 749 | nvidia,pins = "vi_d10_pt2", |
| 750 | "vi_d0_pt4", "pbb0"; |
| 751 | nvidia,function = "rsvd2"; |
| 752 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 753 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 754 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 755 | }; |
| 756 | |
| 757 | kb_row0_pr0 { |
| 758 | nvidia,pins = "kb_row0_pr0"; |
| 759 | nvidia,function = "rsvd4"; |
| 760 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 761 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 762 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 763 | }; |
| 764 | |
| 765 | gmi_ad0_pg0 { |
| 766 | nvidia,pins = "gmi_ad0_pg0", |
| 767 | "gmi_ad1_pg1", |
| 768 | "gmi_ad2_pg2", |
| 769 | "gmi_ad3_pg3", |
| 770 | "gmi_ad6_pg6", |
| 771 | "gmi_ad7_pg7", |
| 772 | "gmi_wr_n_pi0", |
| 773 | "gmi_oe_n_pi1", |
| 774 | "gmi_dqs_pi2", |
| 775 | "gmi_adv_n_pk0", |
| 776 | "gmi_clk_pk1"; |
| 777 | nvidia,function = "nand"; |
| 778 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 779 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 780 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 781 | }; |
| 782 | |
| 783 | gmi_ad13_ph5 { |
| 784 | nvidia,pins = "gmi_ad13_ph5"; |
| 785 | nvidia,function = "nand"; |
| 786 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 787 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 788 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 789 | }; |
| 790 | |
| 791 | gmi_ad10_ph2 { |
| 792 | nvidia,pins = "gmi_ad10_ph2", |
| 793 | "gmi_ad11_ph3", |
| 794 | "gmi_ad14_ph6"; |
| 795 | nvidia,function = "nand"; |
| 796 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 797 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 798 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 799 | }; |
| 800 | |
| 801 | gmi_ad12_ph4 { |
| 802 | nvidia,pins = "gmi_ad12_ph4", |
| 803 | "gmi_rst_n_pi4", |
| 804 | "gmi_cs7_n_pi6"; |
| 805 | nvidia,function = "nand"; |
| 806 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 807 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 808 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 809 | }; |
| 810 | |
| 811 | /* Vibrator control */ |
| 812 | vibrator { |
| 813 | nvidia,pins = "gmi_ad15_ph7"; |
| 814 | nvidia,function = "nand"; |
| 815 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 816 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 817 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 818 | }; |
| 819 | |
| 820 | /* PWM pimnmux */ |
| 821 | pwm_0 { |
| 822 | nvidia,pins = "gmi_ad8_ph0"; |
| 823 | nvidia,function = "pwm0"; |
| 824 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 825 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 826 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 827 | }; |
| 828 | pwm_1 { |
| 829 | nvidia,pins = "gmi_ad9_ph1"; |
| 830 | nvidia,function = "pwm1"; |
| 831 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 832 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 833 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 834 | }; |
| 835 | pwm_2 { |
| 836 | nvidia,pins = "pu5"; |
| 837 | nvidia,function = "pwm2"; |
| 838 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 839 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 840 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 841 | }; |
| 842 | |
| 843 | gmi_cs6_n_pi3 { |
| 844 | nvidia,pins = "gmi_cs6_n_pi3"; |
| 845 | nvidia,function = "gmi"; |
| 846 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 847 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 848 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 849 | }; |
| 850 | |
| 851 | /* Spdif pinmux */ |
| 852 | spdif_out { |
| 853 | nvidia,pins = "spdif_out_pk5"; |
| 854 | nvidia,function = "spdif"; |
| 855 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 856 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 857 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 858 | }; |
| 859 | |
| 860 | spdif_in { |
| 861 | nvidia,pins = "spdif_in_pk6"; |
| 862 | nvidia,function = "spdif"; |
| 863 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 864 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 865 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 866 | }; |
| 867 | |
| 868 | vi_d4_pl2 { |
| 869 | nvidia,pins = "vi_d4_pl2"; |
| 870 | nvidia,function = "vi"; |
| 871 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 872 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 873 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 874 | }; |
| 875 | |
| 876 | vi_d6_pl4 { |
| 877 | nvidia,pins = "vi_d6_pl4"; |
| 878 | nvidia,function = "vi"; |
| 879 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 880 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 881 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Svyatoslav Ryhel | cc81ef9 | 2024-01-20 15:06:23 +0200 | [diff] [blame] | 882 | nvidia,lock = <1>; |
| 883 | nvidia,io-reset = <1>; |
Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 884 | }; |
| 885 | |
| 886 | vi_mclk_pt1 { |
| 887 | nvidia,pins = "vi_mclk_pt1"; |
| 888 | nvidia,function = "vi"; |
| 889 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 890 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 891 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 892 | }; |
| 893 | |
| 894 | jtag_rtck { |
| 895 | nvidia,pins = "jtag_rtck_pu7"; |
| 896 | nvidia,function = "rtck"; |
| 897 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 898 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 899 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 900 | }; |
| 901 | |
| 902 | crt_hsync_pv6 { |
| 903 | nvidia,pins = "crt_hsync_pv6", |
| 904 | "crt_vsync_pv7"; |
| 905 | nvidia,function = "crt"; |
| 906 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 907 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 908 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 909 | }; |
| 910 | |
| 911 | clk1_out { |
| 912 | nvidia,pins = "clk1_out_pw4"; |
| 913 | nvidia,function = "extperiph1"; |
| 914 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 915 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 916 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 917 | }; |
| 918 | |
| 919 | clk2_out { |
| 920 | nvidia,pins = "clk2_out_pw5"; |
| 921 | nvidia,function = "extperiph2"; |
| 922 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 923 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 924 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 925 | }; |
| 926 | |
| 927 | clk3_out { |
| 928 | nvidia,pins = "clk3_out_pee0"; |
| 929 | nvidia,function = "extperiph3"; |
| 930 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 931 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 932 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 933 | }; |
| 934 | |
| 935 | sys_clk_req { |
| 936 | nvidia,pins = "sys_clk_req_pz5"; |
| 937 | nvidia,function = "sysclk"; |
| 938 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 939 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 940 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 941 | }; |
| 942 | |
| 943 | pbb4 { |
| 944 | nvidia,pins = "pbb4"; |
| 945 | nvidia,function = "vgp4"; |
| 946 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 947 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 948 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 949 | }; |
| 950 | |
| 951 | pbb5 { |
| 952 | nvidia,pins = "pbb5"; |
| 953 | nvidia,function = "vgp5"; |
| 954 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 955 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 956 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 957 | }; |
| 958 | |
| 959 | pbb6 { |
| 960 | nvidia,pins = "pbb6"; |
| 961 | nvidia,function = "vgp6"; |
| 962 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 963 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 964 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 965 | }; |
| 966 | |
| 967 | clk2_req_pcc5 { |
| 968 | nvidia,pins = "clk2_req_pcc5", |
| 969 | "clk1_req_pee2"; |
| 970 | nvidia,function = "dap"; |
| 971 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 972 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 973 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 974 | }; |
| 975 | |
| 976 | clk3_req_pee1 { |
| 977 | nvidia,pins = "clk3_req_pee1"; |
| 978 | nvidia,function = "dev3"; |
| 979 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 980 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 981 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 982 | }; |
| 983 | |
| 984 | owr { |
| 985 | nvidia,pins = "owr"; |
| 986 | nvidia,function = "owr"; |
| 987 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 988 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 989 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 990 | }; |
| 991 | |
| 992 | /* GPIO power/drive control */ |
| 993 | drive_dap1 { |
| 994 | nvidia,pins = "drive_dap1", |
| 995 | "drive_dap2", |
| 996 | "drive_dbg", |
| 997 | "drive_at5", |
| 998 | "drive_gme", |
| 999 | "drive_ddc", |
| 1000 | "drive_ao1", |
| 1001 | "drive_uart3"; |
| 1002 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
| 1003 | nvidia,schmitt = <TEGRA_PIN_ENABLE>; |
| 1004 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| 1005 | nvidia,pull-down-strength = <31>; |
| 1006 | nvidia,pull-up-strength = <31>; |
| 1007 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 1008 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 1009 | }; |
| 1010 | |
| 1011 | drive_sdio1 { |
| 1012 | nvidia,pins = "drive_sdio1", |
| 1013 | "drive_sdio3"; |
| 1014 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
| 1015 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 1016 | nvidia,pull-down-strength = <46>; |
| 1017 | nvidia,pull-up-strength = <42>; |
| 1018 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; |
| 1019 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; |
| 1020 | }; |
| 1021 | }; |
| 1022 | }; |
| 1023 | |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1024 | uarta: serial@70006000 { |
| 1025 | status = "okay"; |
| 1026 | }; |
| 1027 | |
| 1028 | pwm: pwm@7000a000 { |
| 1029 | status = "okay"; |
| 1030 | }; |
| 1031 | |
| 1032 | gen1_i2c: i2c@7000c000 { |
| 1033 | status = "okay"; |
| 1034 | clock-frequency = <100000>; |
| 1035 | }; |
| 1036 | |
| 1037 | pwr_i2c: i2c@7000d000 { |
| 1038 | status = "okay"; |
| 1039 | clock-frequency = <400000>; |
| 1040 | |
| 1041 | /* Texas Instruments TPS659110 PMIC */ |
| 1042 | pmic: tps65911@2d { |
| 1043 | compatible = "ti,tps65911"; |
| 1044 | reg = <0x2d>; |
| 1045 | |
| 1046 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 1047 | #interrupt-cells = <2>; |
| 1048 | interrupt-controller; |
| 1049 | |
| 1050 | ti,system-power-controller; |
| 1051 | |
| 1052 | #gpio-cells = <2>; |
| 1053 | gpio-controller; |
| 1054 | |
| 1055 | regulators { |
Svyatoslav Ryhel | a2b3f64 | 2023-10-03 09:36:38 +0300 | [diff] [blame] | 1056 | vdd_1v8_vio: vddio { |
| 1057 | regulator-name = "vdd_1v8_gen"; |
| 1058 | regulator-min-microvolt = <1800000>; |
| 1059 | regulator-max-microvolt = <1800000>; |
| 1060 | regulator-always-on; |
| 1061 | regulator-boot-on; |
| 1062 | }; |
| 1063 | |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1064 | /* eMMC VDD */ |
| 1065 | vcore_emmc: ldo1 { |
| 1066 | regulator-name = "vdd_emmc_core"; |
Svyatoslav Ryhel | a2b3f64 | 2023-10-03 09:36:38 +0300 | [diff] [blame] | 1067 | regulator-min-microvolt = <3300000>; |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1068 | regulator-max-microvolt = <3300000>; |
Svyatoslav Ryhel | bf73217 | 2023-08-26 18:39:29 +0300 | [diff] [blame] | 1069 | regulator-boot-on; |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1070 | }; |
| 1071 | |
| 1072 | /* uSD slot VDD */ |
| 1073 | vdd_usd: ldo2 { |
| 1074 | regulator-name = "vdd_usd"; |
| 1075 | regulator-min-microvolt = <3100000>; |
| 1076 | regulator-max-microvolt = <3100000>; |
Svyatoslav Ryhel | bf73217 | 2023-08-26 18:39:29 +0300 | [diff] [blame] | 1077 | regulator-boot-on; |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1078 | }; |
| 1079 | |
| 1080 | /* uSD slot VDDIO */ |
| 1081 | vddio_usd: ldo3 { |
| 1082 | regulator-name = "vddio_usd"; |
Svyatoslav Ryhel | a2b3f64 | 2023-10-03 09:36:38 +0300 | [diff] [blame] | 1083 | regulator-min-microvolt = <3100000>; |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1084 | regulator-max-microvolt = <3100000>; |
Svyatoslav Ryhel | a2b3f64 | 2023-10-03 09:36:38 +0300 | [diff] [blame] | 1085 | regulator-always-on; |
| 1086 | regulator-boot-on; |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1087 | }; |
| 1088 | }; |
| 1089 | }; |
| 1090 | }; |
| 1091 | |
| 1092 | sdmmc1: sdhci@78000000 { |
| 1093 | status = "okay"; |
| 1094 | bus-width = <4>; |
| 1095 | |
| 1096 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 1097 | power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; |
| 1098 | |
| 1099 | vmmc-supply = <&vdd_usd>; |
| 1100 | vqmmc-supply = <&vddio_usd>; |
| 1101 | }; |
| 1102 | |
| 1103 | sdmmc4: sdhci@78000600 { |
| 1104 | status = "okay"; |
| 1105 | bus-width = <8>; |
| 1106 | non-removable; |
Svyatoslav Ryhel | a2b3f64 | 2023-10-03 09:36:38 +0300 | [diff] [blame] | 1107 | |
| 1108 | vmmc-supply = <&vcore_emmc>; |
| 1109 | vqmmc-supply = <&vdd_1v8_vio>; |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1110 | }; |
| 1111 | |
| 1112 | /* USB via ASUS connector */ |
| 1113 | usb1: usb@7d000000 { |
| 1114 | status = "okay"; |
| 1115 | dr_mode = "otg"; |
| 1116 | }; |
| 1117 | |
Svyatoslav Ryhel | 6c43861 | 2023-08-25 20:23:14 +0300 | [diff] [blame] | 1118 | usb-phy@7d000000 { |
| 1119 | status = "okay"; |
| 1120 | nvidia,hssync-start-delay = <0>; |
| 1121 | nvidia,xcvr-lsfslew = <2>; |
| 1122 | nvidia,xcvr-lsrslew = <2>; |
| 1123 | }; |
| 1124 | |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1125 | /* Dock's USB port */ |
| 1126 | usb3: usb@7d008000 { |
| 1127 | status = "okay"; |
| 1128 | }; |
| 1129 | |
Svyatoslav Ryhel | b97e5a8 | 2023-10-03 09:36:35 +0300 | [diff] [blame] | 1130 | usb-phy@7d008000 { |
| 1131 | status = "okay"; |
| 1132 | }; |
| 1133 | |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1134 | backlight: backlight { |
| 1135 | compatible = "pwm-backlight"; |
| 1136 | |
| 1137 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| 1138 | power-supply = <&vdd_5v0_bl>; |
| 1139 | pwms = <&pwm 0 4000000>; |
| 1140 | |
| 1141 | brightness-levels = <1 35 70 105 140 175 210 255>; |
| 1142 | default-brightness-level = <5>; |
| 1143 | }; |
| 1144 | |
| 1145 | /* PMIC has a built-in 32KHz oscillator which is used by PMC */ |
| 1146 | clk32k_in: clock-32k { |
| 1147 | compatible = "fixed-clock"; |
| 1148 | #clock-cells = <0>; |
| 1149 | clock-frequency = <32768>; |
| 1150 | clock-output-names = "pmic-oscillator"; |
| 1151 | }; |
| 1152 | |
Svyatoslav Ryhel | 8e56624 | 2024-01-31 10:08:06 +0200 | [diff] [blame^] | 1153 | extcon-keys { |
| 1154 | compatible = "gpio-keys"; |
| 1155 | |
| 1156 | switch-dock-hall-sensor { |
| 1157 | label = "Lid sensor"; |
| 1158 | gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; |
| 1159 | linux,code = <SW_LID>; |
| 1160 | }; |
| 1161 | }; |
| 1162 | |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1163 | gpio-keys { |
| 1164 | compatible = "gpio-keys"; |
| 1165 | |
| 1166 | key-power { |
| 1167 | label = "Power"; |
| 1168 | gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; |
| 1169 | linux,code = <KEY_ENTER>; |
| 1170 | }; |
| 1171 | |
| 1172 | key-volume-up { |
| 1173 | label = "Volume Up"; |
| 1174 | gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; |
| 1175 | linux,code = <KEY_UP>; |
| 1176 | }; |
| 1177 | |
| 1178 | key-volume-down { |
| 1179 | label = "Volume Down"; |
| 1180 | gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; |
| 1181 | linux,code = <KEY_DOWN>; |
| 1182 | }; |
| 1183 | }; |
| 1184 | |
| 1185 | panel: panel { |
| 1186 | compatible = "simple-panel"; |
| 1187 | |
| 1188 | power-supply = <&vdd_pnl_reg>; |
| 1189 | enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; |
| 1190 | |
| 1191 | backlight = <&backlight>; |
| 1192 | |
| 1193 | display-timings { |
| 1194 | timing@0 { |
| 1195 | /* 1280x800@60Hz */ |
| 1196 | clock-frequency = <68000000>; |
| 1197 | |
| 1198 | hactive = <1280>; |
| 1199 | hfront-porch = <48>; |
| 1200 | hback-porch = <18>; |
| 1201 | hsync-len = <30>; |
| 1202 | |
| 1203 | vactive = <800>; |
| 1204 | vfront-porch = <3>; |
| 1205 | vback-porch = <12>; |
| 1206 | vsync-len = <5>; |
| 1207 | }; |
| 1208 | }; |
| 1209 | }; |
| 1210 | |
| 1211 | vdd_pnl_reg: regulator-pnl { |
| 1212 | compatible = "regulator-fixed"; |
| 1213 | regulator-name = "vdd_panel"; |
| 1214 | regulator-min-microvolt = <3300000>; |
| 1215 | regulator-max-microvolt = <3300000>; |
| 1216 | gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; |
| 1217 | enable-active-high; |
| 1218 | }; |
| 1219 | |
| 1220 | vdd_5v0_bl: regulator-bl { |
| 1221 | compatible = "regulator-fixed"; |
| 1222 | regulator-name = "vdd_5v0_bl"; |
| 1223 | regulator-min-microvolt = <5000000>; |
| 1224 | regulator-max-microvolt = <5000000>; |
Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1225 | gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; |
| 1226 | enable-active-high; |
| 1227 | }; |
| 1228 | }; |