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git01.mediatek.com / filogic / uboot / 8e4c71fe034692d4b75818a4c26516e70684d10c / . / doc / README.dk1s40_std32
blob: 08c8244450b839cd5ef49bdb0d714a729beb0efe [file] [log] [blame]
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]1
2TODO: specify IDE i/f
3 specify OCI
4
5
6===============================================================================
7 C P U , M E M O R Y , I N / O U T C O M P O N E N T S
8===============================================================================
9see also [1]-[5]
10
11CPU: "standard_32"
12 32 bit NIOS for 50 MHz
13 256 Byte for register file (15 levels)
14 4 KByte instruction cache (4 bytes in each cache line)
15 4 KByte data cache (4 bytes in each cache line)
16 2 KByte On Chip ROM with GERMS boot monitor
17 64 KByte On Chip RAM
18 MSTEP multiplier
19 no Debug Core
20 On Chip Instrumentation (OCI) enabled
21
22 U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
23 CFG_NIOS_CPU_ICACHE = 4096
24 CFG_NIOS_CPU_DCACHE = 4096
25 CFG_NIOS_CPU_REG_NUMS = 256
26 CFG_NIOS_CPU_MUL = 0
27 CFG_NIOS_CPU_MSTEP = 1
28 CFG_NIOS_CPU_DBG_CORE = 0
29
30OCI: (TODO)
31
32IRQ: Nr. | used by
33 ------+--------------------------------------------------------
34 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
35 25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25
36 30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30
37 35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35
38 40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40
39 50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50
40
41MEMORY: 8 MByte Flash
42 1 MByte SRAM
43 16 MByte SDRAM
44
45Timer: TIMER0: high priority programmable timer (IRQ16)
46 TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
47
48 U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1
49 CFG_NIOS_CPU_USER_TIMER = 0
50
51PIO: Nr. | description
52 ------+--------------------------------------------------------
53 PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40)
54 PIO1 | LCD: 11 in/outputs for ASCII LCD
55 PIO2 | LED: 8 outputs for user LEDs
56 PIO3 | SEVENSEG: 16 outputs for user seven segment display
57 PIO4 | RECONF: 1 in/output for . . . . . . . . . . . .
58 PIO5 | CFPRESENT: 1 input for CF present event (IRQ35)
59 PIO6 | CFPOWER: 1 output to controll CF power supply
60 PIO7 | CFATASEL: 1 output to controll CF ATA card select
61
62 U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0
63 CFG_NIOS_CPU_LCD_PIO = 1
64 CFG_NIOS_CPU_LED_PIO = 2
65 CFG_NIOS_CPU_SEVENSEG_PIO = 3
66 CFG_NIOS_CPU_RECONF_PIO = 4
67 CFG_NIOS_CPU_CFPRESENT_PIO = 5
68 CFG_NIOS_CPU_CFPOWER_PIO = 6
69 CFG_NIOS_CPU_CFATASEL_PIO = 7
70
71UART: UART0: fixed baudrate of 115200, fixed protocol 8N1,
72 without handshake RTS/CTS (IRQ25)
73
74LAN: SMsC LAN91C111 with:
75 - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
76 - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
77
78IDE: (TODO)
79
80
81===============================================================================
82 M E M O R Y M A P
83===============================================================================
84
85- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - -
86
87 0x02000000 ---32-----------16|15------------0-
88 | : | \
89 | : | |
90 SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE
91 | : | | = 0x01000000
92 | : | /
93 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
94 | |
95 : gap :
96 : :
97
98- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
99
100 : :
101 : gap :
102 | |
103 0x00920a80 ---32-----------16|15------------0-
104 | | | \
105 : (real size : : |
106 IDE i/f : and content : : > 0x00000080
107 [5] : unknown) : : |
108 | | | /
109 0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
110 | (unused) | \
111 + 0x1c |- - - - - - - - - - - - - - - -| |
112 | (unused) | |
113 + 0x18 |- - - - - - - - - - - - - - - -| |
114 | (unused) | |
115 + 0x14 |- - - - - - - - - - - - - - - -| |
116 TIMER1 | (unused) | |
117 [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
118 | (unused) | |
119 + 0x0c |- - - - - - - - - - - - - - - -| |
120 | (unused) | |
121 + 0x08 |- - - - - - - - - - - - - - - -| |
122 | control (1 bit) (rw) | |
123 + 0x04 |- - - - - - - - - - - - - - - -| |
124 | status (2 bit) (rw) | /
125 0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1
126 | (unused) | \
127 + 0x0c |- - - - - - - - - - - - - - - -| |
128 PIO7 | (unused) | |
129 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
130 | (unused) | |
131 + 0x04 |- - - - - - - - - - - - - - - -| |
132 | data (1 bit) (wo) | /
133 0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7
134 | (unused) | \
135 + 0x0c |- - - - - - - - - - - - - - - -| |
136 PIO6 | (unused) | |
137 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
138 | (unused) | |
139 + 0x04 |- - - - - - - - - - - - - - - -| |
140 | data (1 bit) (wo) | /
141 0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6
142 | edgecapture (1 bit) (rw) | \
143 + 0x0c |- - - - - - - - - - - - - - - -| |
144 PIO5 | interruptmask (1 bit) (rw) | |
145 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
146 | (unused) | |
147 + 0x04 |- - - - - - - - - - - - - - - -| |
148 | data (1 bit) (ro) | /
149 0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5
150 | (unused) | \
151 + 0x0c |- - - - - - - - - - - - - - - -| |
152 PIO4 | (unused) | |
153 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
154 | direction (1 bit) (rw) | |
155 + 0x04 |- - - - - - - - - - - - - - - -| |
156 | data (1 bit) (rw) | /
157 0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4
158 | (unused) | \
159 + 0x0c |- - - - - - - - - - - - - - - -| |
160 PIO3 | (unused) | |
161 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
162 | (unused) | |
163 + 0x04 |- - - - - - - - - - - - - - - -| |
164 | data (16 bit) (wo) | /
165 0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
166 | (unused) | \
167 + 0x0c |- - - - - - - - - - - - - - - -| |
168 PIO2 | (unused) | |
169 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
170 | (unused) | |
171 + 0x04 |- - - - - - - - - - - - - - - -| |
172 | data (8 bit) (wo) | /
173 0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
174 | (unused) | \
175 + 0x0c |- - - - - - - - - - - - - - - -| |
176 PIO1 | (unused) | |
177 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
178 | direction (11 bit) (rw) | |
179 + 0x04 |- - - - - - - - - - - - - - - -| |
180 | data (11 bit) (rw) | /
181 0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
182 | edgecapture (4 bit) (rw) | \
183 + 0x0c |- - - - - - - - - - - - - - - -| |
184 PIO0 | interruptmask (4 bit) (rw) | |
185 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
186 | (unused) | |
187 + 0x04 |- - - - - - - - - - - - - - - -| |
188 | data (4 bit) (ro) | /
189 0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
190 | (unused) | \
191 + 0x1c |- - - - - - - - - - - - - - - -| |
192 | (unused) | |
193 + 0x18 |- - - - - - - - - - - - - - - -| |
194 | snaph (16 bit) (rw) | |
195 + 0x14 |- - - - - - - - - - - - - - - -| |
196 TIMER0 | snapl (16 bit) (rw) | |
197 [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
198 | periodh (16 bit) (rw) | |
199 + 0x0c |- - - - - - - - - - - - - - - -| |
200 | periodl (16 bit) (rw) | |
201 + 0x08 |- - - - - - - - - - - - - - - -| |
202 | control (4 bit) (rw) | |
203 + 0x04 |- - - - - - - - - - - - - - - -| |
204 | status (2 bit) (rw) | /
205 0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
206 | | \
207 : gap : > (space for UART1)
208 | | /
209 0x00920920 ---32-----------16|15------------0-
210 | (unused) | \
211 + 0x1c |- - - - - - - - - - - - - - - -| |
212 | (unused) | |
213 + 0x18 |- - - - - - - - - - - - - - - -| |
214 | (unused) | |
215 + 0x14 |- - - - - - - - - - - - - - - -| |
216 UART0 | (unused) | > 0x00000020
217 [2] + 0x10 |- - - - - - - - - - - - - - - -| |
218 | control (10 bit) (rw) | |
219 + 0x0c |- - - - - - - - - - - - - - - -| |
220 | status (10 bit) (rw) | |
221 + 0x08 |- - - - - - - - - - - - - - - -| |
222 | txdata (8 bit) (wo) | |
223 + 0x04 |- - - - - - - - - - - - - - - -| |
224 | rxdata (8 bit) (ro) | /
225 0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
226
227- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - -
228
229 0x00920900 -----------------------------------
230 | | \
231 : (real size : |
232 OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE
233 : unknown) : | = 0x00000100
234 | | /
235 0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE
236
237- - - - - - - - - - - on chip memory 2 - - - - - - - - - - -
238
239 0x00920800 ---32-----------16|15------------0-
240 | : | \
241 | : | |
242 GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
243 | : | | = 0x00000800
244 | : | /
245 0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
246 0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
247
248- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
249
250 0x00920000 ---32-----------16|15------------0-
251 | gap | \
252 0x00910310 --+-------------------------------| |
253 | | |
254 | register bank (size = 0x10) | |
255 | +--------.---.---.--- | |
256 | | bank 0 \ 1 \ 2 \ 3 \ | |
257 | |---------------------------+ | |
258 LAN91C111 | | BANK | RESERVED | | |
259 | |- - - - - - -|- - - - - - -| | > na_lan91c111_size
260 | | RPCR | MIR | | | = 0x00010000
261 | |- - - - - - -|- - - - - - -| | |
262 | | COUNTER | RCR | | |
263 | |- - - - - - -|- - - - - - -| | |
264 | | EPH STATUS | TCR | | |
265 | +---------------------------+ | |
266 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
267 | gap | /
268 0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
269
270- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
271
272 0x00910000 ---32-----------16|15------------0-
273 | : | \
274 | : | |
275 onchip RAM | : | > CFG_NIOS_CPU_RAM_SIZE
276 | : | | = 0x00010000
277 | : | /
278 0x00900000 ---32-----------16|15------------0- CFG_NIOS_CPU_RAM_BASE
279
280- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - -
281
282 0x00900000 ---32-----------16|15------------0-
283 0x00900000 --+32-----------16|15------------0+
284 | . | \ \
285 | . | | |
286 | . | | > CFG_NIOS_CPU_VEC_SIZE
287 | . | | | = 0x00000100
288 | . | | /
289 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
290 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK
291 | . | | \
292 | . | | |
293 | . | | > stack area
294 | . | | |
295 | . | | V
296 | . | |
297 SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE
298 | . | | = 0x00100000
299 | | /
300 0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
301 0x00800000 ---8-------------4|3-------------0-
302 | sector 127 | \
303 + 0x7f0000 |- - - - - - - - - - - - - - - -| |
304 | : | |
305 Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
306 | sector 1 : | | = 0x00800000
307 + 0x010000 |- - - - - - - - - - - - - - - -| |
308 | sector 0 (size = 0x10000) | /
309 0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
310
311
312===============================================================================
313 F L A S H M E M O R Y A L L O C A T I O N
314===============================================================================
315
316 0x00800000 ---8-------------4|3-------------0-
317 | : | \
318 | : | |
319 SAFE | : | > 2 MByte
320 FPGA conf. | : | | (NOT usable by software)
321 | : | /
322 0x00600000 --+- - - - - - - -:- - - - - - - -+-
323 | : | \
324 | : | |
325 USER | : | > 2 MByte
326 FPGA conf. | : | | (NOT usable by software)
327 | : | /
328 0x00400000 --+- - - - - - - -:- - - - - - - -+-
329 | : | \
330 | : | |
331 WEB pages | : | > 2 MByte
332 | : | | (provisory usable)
333 | : | /
334 0x00200000 --+- - - - - - - -:- - - - - - - -+-
335 | : | \
336 | : | |
337 | : | > 2 MByte free for use
338 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
339 | : | /
340 0x00000000 ---8-------------4|3-------------0-
341
342
343===============================================================================
344 R E F E R E N C E S
345===============================================================================
346[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s40.pdf
347[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
348[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
349[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
350[5] http://www.opencores.org/projects/ata/
351 http://www.t13.org/index.html
352
353
354===============================================================================
355Stephan Linz <linz@li-pro.net>