| Simon Glass | e42bff5 | 2020-09-22 12:44:48 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2016 Intel Corporation. |
| 4 | */ |
| 5 | |
| 6 | /* XHCI Controller 0:15.0 */ |
| 7 | Device (XHCI) { |
| 8 | Name (_ADR, 0x00150000) /* Device 21, Function 0 */ |
| 9 | |
| 10 | Name (_S3D, 3) /* D3 supported in S3 */ |
| 11 | Name (_S0W, 3) /* D3 can wake device in S0 */ |
| 12 | Name (_S3W, 3) /* D3 can wake system from S3 */ |
| 13 | |
| 14 | /* Declare XHCI GPE status and enable bits are bit 13 */ |
| 15 | Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 }) |
| 16 | |
| 17 | Method (_STA, 0) |
| 18 | { |
| 19 | Return (0xF) |
| 20 | } |
| 21 | |
| 22 | Device (RHUB) |
| 23 | { |
| 24 | /* Root Hub */ |
| 25 | Name (_ADR, Zero) |
| 26 | |
| 27 | #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) |
| 28 | #include "xhci_glk_ports.asl" |
| 29 | #else |
| 30 | #include "xhci_apl_ports.asl" |
| 31 | #endif |
| 32 | } |
| 33 | } |