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Chunhe Lan2016d452013-06-14 16:21:48 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Authors: Roy Zang <tie-fei.zang@freescale.com>
5 * Chunhe Lan <Chunhe.Lan@freescale.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Chunhe Lan2016d452013-06-14 16:21:48 +08008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Chunhe Lan2016d452013-06-14 16:21:48 +080013#ifndef CONFIG_SYS_MONITOR_BASE
14#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
15#endif
16
17#ifndef CONFIG_RESET_VECTOR_ADDRESS
18#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
19#endif
20
21/* High Level Configuration Options */
Chunhe Lan2016d452013-06-14 16:21:48 +080022#define CONFIG_MP /* support multiple processors */
23
Chunhe Lan2016d452013-06-14 16:21:48 +080024#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Robert P. J. Daya8099812016-05-03 19:52:49 -040025#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
26#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
27#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
Chunhe Lan2016d452013-06-14 16:21:48 +080028#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
29#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
30#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
Chunhe Lan2016d452013-06-14 16:21:48 +080031
32#ifndef __ASSEMBLY__
33extern unsigned long get_clock_freq(void);
34#endif
35
36#define CONFIG_SYS_CLK_FREQ 66666666
37#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
38
39/*
40 * These can be toggled for performance analysis, otherwise use default.
41 */
42#define CONFIG_L2_CACHE /* toggle L2 cache */
43#define CONFIG_BTB /* toggle branch predition */
44#define CONFIG_HWCONFIG
45
46#define CONFIG_ENABLE_36BIT_PHYS
47
48#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
49#define CONFIG_SYS_MEMTEST_END 0x02000000
50
Chunhe Lan2016d452013-06-14 16:21:48 +080051/* Implement conversion of addresses in the LBC */
52#define CONFIG_SYS_LBC_LBCR 0x00000000
53#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
54
55/* DDR Setup */
56#define CONFIG_VERY_BIG_RAM
57#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
58#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
59
60#define CONFIG_DIMM_SLOTS_PER_CTLR 1
61#define CONFIG_CHIP_SELECTS_PER_CTRL 1
62
63#define CONFIG_DDR_SPD
Chunhe Lan2016d452013-06-14 16:21:48 +080064#define CONFIG_FSL_DDR_INTERACTIVE
65#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
66#define CONFIG_SYS_SPD_BUS_NUM 0
67#define SPD_EEPROM_ADDRESS 0x50
68#define CONFIG_SYS_DDR_RAW_TIMING
69
70/*
71 * Memory map
72 *
73 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
74 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
75 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
76 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
77 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
78 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
79 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
80 *
81 * Localbus non-cacheable
82 *
83 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
84 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
85 */
86
87/*
88 * Local Bus Definitions
89 */
90#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
91#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
92
93#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
94 | BR_PS_16 | BR_V)
95#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
96
97#define CONFIG_FLASH_CFI_DRIVER
98#define CONFIG_SYS_FLASH_CFI
99#define CONFIG_SYS_FLASH_EMPTY_INFO
100#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
101#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
102#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
103#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
104
Chunhe Lan2016d452013-06-14 16:21:48 +0800105#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
106
107#define CONFIG_SYS_INIT_RAM_LOCK
108#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
109#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
110#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
111 GENERATED_GBL_DATA_SIZE)
112#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
113
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530114#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */
Chunhe Lan2016d452013-06-14 16:21:48 +0800115#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
116
117#define CONFIG_SYS_NAND_BASE 0xffa00000
118#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
119
120#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
121#define CONFIG_SYS_MAX_NAND_DEVICE 1
Chunhe Lan2016d452013-06-14 16:21:48 +0800122#define CONFIG_NAND_FSL_ELBC
123#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
124
125/* NAND flash config */
126#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
127 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
128 | BR_PS_8 /* Port Size = 8bit */ \
129 | BR_MS_FCM /* MSEL = FCM */ \
130 | BR_V) /* valid */
131#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
132 | OR_FCM_PGS \
133 | OR_FCM_CSCT \
134 | OR_FCM_CST \
135 | OR_FCM_CHT \
136 | OR_FCM_SCY_1 \
137 | OR_FCM_TRLX \
138 | OR_FCM_EHTR)
139
140#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
141#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
142#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
143#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
144
145/* Serial Port */
146#define CONFIG_CONS_INDEX 1
147#undef CONFIG_SERIAL_SOFTWARE_FIFO
Chunhe Lan2016d452013-06-14 16:21:48 +0800148#define CONFIG_SYS_NS16550_SERIAL
149#define CONFIG_SYS_NS16550_REG_SIZE 1
150#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
151
152#define CONFIG_SYS_BAUDRATE_TABLE \
153 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
154
155#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
156#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
157
Chunhe Lan2016d452013-06-14 16:21:48 +0800158/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200159#define CONFIG_SYS_I2C
160#define CONFIG_SYS_I2C_FSL
161#define CONFIG_SYS_FSL_I2C_SPEED 400000
162#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
163#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
164#define CONFIG_SYS_FSL_I2C2_SPEED 400000
165#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
166#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Chunhe Lan2016d452013-06-14 16:21:48 +0800167
168/*
169 * I2C2 EEPROM
170 */
171#define CONFIG_ID_EEPROM
172#ifdef CONFIG_ID_EEPROM
173#define CONFIG_SYS_I2C_EEPROM_NXID
174#endif
175#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
176#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
177#define CONFIG_SYS_EEPROM_BUS_NUM 0
178
Chunhe Lan2016d452013-06-14 16:21:48 +0800179/*
180 * General PCI
181 * Memory space is mapped 1-1, but I/O space must start from 0.
182 */
183
184/* controller 3, Slot 1, tgtid 3, Base address b000 */
185#define CONFIG_SYS_PCIE3_NAME "Slot 3"
186#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
187#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
188#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
189#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
190#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
191#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
192#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
193#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
194
195/* controller 2, direct to uli, tgtid 2, Base address 9000 */
196#define CONFIG_SYS_PCIE2_NAME "Slot 2"
197#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
198#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
199#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
200#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
201#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
202#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
203#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
204#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
205
206/* controller 1, Slot 2, tgtid 1, Base address a000 */
207#define CONFIG_SYS_PCIE1_NAME "Slot 1"
208#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
209#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
210#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
211#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
212#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
213#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
214#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
215#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
216
217#if defined(CONFIG_PCI)
Chunhe Lan2016d452013-06-14 16:21:48 +0800218#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
219#endif /* CONFIG_PCI */
220
221/*
222 * Environment
223 */
224#define CONFIG_ENV_OVERWRITE
225
Chunhe Lan2016d452013-06-14 16:21:48 +0800226#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Chunhe Lan2016d452013-06-14 16:21:48 +0800227#define CONFIG_ENV_SIZE 0x2000
228#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
229
230#define CONFIG_LOADS_ECHO /* echo on for serial download */
231#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
232
233/*
Chunhe Lan2016d452013-06-14 16:21:48 +0800234 * USB
235 */
236#define CONFIG_HAS_FSL_DR_USB
237#ifdef CONFIG_HAS_FSL_DR_USB
Tom Riniceed5d22017-05-12 22:33:27 -0400238#ifdef CONFIG_USB_EHCI_HCD
Chunhe Lan2016d452013-06-14 16:21:48 +0800239#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
240#define CONFIG_USB_EHCI_FSL
Chunhe Lan2016d452013-06-14 16:21:48 +0800241#endif
242#endif
243
244/*
245 * Miscellaneous configurable options
246 */
Chunhe Lan2016d452013-06-14 16:21:48 +0800247#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Chunhe Lan2016d452013-06-14 16:21:48 +0800248
249/*
250 * For booting Linux, the board info and command line data
251 * have to be in the first 64 MB of memory, since this is
252 * the maximum mapped by the Linux kernel during initialization.
253 */
254#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
255#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
256
257/*
258 * Environment Configuration
259 */
260#define CONFIG_BOOTFILE "uImage"
261#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
262
263/* default location for tftp and bootm */
264#define CONFIG_LOADADDR 1000000
265
Chunhe Lan2016d452013-06-14 16:21:48 +0800266/* Qman/Bman */
Chunhe Lan2016d452013-06-14 16:21:48 +0800267#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
268#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
269#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500270#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
271#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
272#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
273#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
274#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
275 CONFIG_SYS_QMAN_CENA_SIZE)
276#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
277#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Chunhe Lan2016d452013-06-14 16:21:48 +0800278#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
279#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
280#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500281#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
282#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
283#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
284#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
285#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
286 CONFIG_SYS_BMAN_CENA_SIZE)
287#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
288#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Chunhe Lan2016d452013-06-14 16:21:48 +0800289
290/* For FM */
291#define CONFIG_SYS_DPAA_FMAN
Chunhe Lan2016d452013-06-14 16:21:48 +0800292
293#ifdef CONFIG_SYS_DPAA_FMAN
294#define CONFIG_FMAN_ENET
295#define CONFIG_PHY_ATHEROS
296#endif
297
298/* Default address of microcode for the Linux Fman driver */
299/* QE microcode/firmware address */
300#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiang83a90842014-03-21 16:21:44 +0800301#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Chunhe Lan2016d452013-06-14 16:21:48 +0800302#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
303#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
304
305#ifdef CONFIG_FMAN_ENET
306#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
307#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
308
309#define CONFIG_SYS_TBIPA_VALUE 8
310#define CONFIG_MII /* MII PHY management */
311#define CONFIG_ETHPRIME "FM1@DTSEC1"
312#endif
313
314#define CONFIG_EXTRA_ENV_SETTINGS \
Chunhe Lan2cd7cd22014-10-17 16:24:06 +0800315 "netdev=eth0\0" \
316 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
317 "loadaddr=1000000\0" \
318 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
319 "tftpflash=tftpboot $loadaddr $uboot; " \
320 "protect off $ubootaddr +$filesize; " \
321 "erase $ubootaddr +$filesize; " \
322 "cp.b $loadaddr $ubootaddr $filesize; " \
323 "protect on $ubootaddr +$filesize; " \
324 "cmp.b $loadaddr $ubootaddr $filesize\0" \
325 "consoledev=ttyS0\0" \
326 "ramdiskaddr=2000000\0" \
327 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500328 "fdtaddr=1e00000\0" \
Chunhe Lan2cd7cd22014-10-17 16:24:06 +0800329 "fdtfile=p1023rdb.dtb\0" \
330 "othbootargs=ramdisk_size=600000\0" \
331 "bdev=sda1\0" \
Chunhe Lan2016d452013-06-14 16:21:48 +0800332 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
333
Chunhe Lan2cd7cd22014-10-17 16:24:06 +0800334#define CONFIG_HDBOOT \
335 "setenv bootargs root=/dev/$bdev rw " \
336 "console=$consoledev,$baudrate $othbootargs;" \
337 "tftp $loadaddr $bootfile;" \
338 "tftp $fdtaddr $fdtfile;" \
339 "bootm $loadaddr - $fdtaddr"
340
341#define CONFIG_NFSBOOTCOMMAND \
342 "setenv bootargs root=/dev/nfs rw " \
343 "nfsroot=$serverip:$rootpath " \
344 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
345 "console=$consoledev,$baudrate $othbootargs;" \
346 "tftp $loadaddr $bootfile;" \
347 "tftp $fdtaddr $fdtfile;" \
348 "bootm $loadaddr - $fdtaddr"
349
350#define CONFIG_RAMBOOTCOMMAND \
351 "setenv bootargs root=/dev/ram rw " \
352 "console=$consoledev,$baudrate $othbootargs;" \
353 "tftp $ramdiskaddr $ramdiskfile;" \
354 "tftp $loadaddr $bootfile;" \
355 "tftp $fdtaddr $fdtfile;" \
356 "bootm $loadaddr $ramdiskaddr $fdtaddr"
357
358#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
359
Chunhe Lan2016d452013-06-14 16:21:48 +0800360#endif /* __CONFIG_H */