blob: 7f854c524fe6e2d43d4af077210600a5a1164993 [file] [log] [blame]
wdenk9c53f402003-10-15 23:53:47 +00001/*
Kumar Galaa9db4ec2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk9c53f402003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk9c53f402003-10-15 23:53:47 +00007 */
8
wdenk13eb2212004-07-09 23:27:13 +00009/*
10 * mpc8560ads board configuration file
11 *
12 * Please refer to doc/README.mpc85xx for more info.
13 *
14 * Make sure you change the MAC address and other network params first,
Joe Hershberger76f353e2015-05-04 14:55:14 -050015 * search for CONFIG_SERVERIP, etc. in this file.
wdenk9c53f402003-10-15 23:53:47 +000016 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/* High Level Configuration Options */
Jon Loeligerf5ad3782005-07-23 10:37:35 -050022#define CONFIG_CPM2 1 /* has CPM2 */
wdenk9c53f402003-10-15 23:53:47 +000023
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020024/*
25 * default CCARBAR is at 0xff700000
26 * assume U-Boot is less than 0.5MB
27 */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020028
Gabor Juhosb4458732013-05-30 07:06:12 +000029#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala7738d5c2008-10-21 11:33:58 -050030#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denka1be4762008-05-20 16:00:29 +020031#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Fleming8ed11962007-05-08 17:27:43 -050032#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
wdenk9c53f402003-10-15 23:53:47 +000033#define CONFIG_ENV_OVERWRITE
Peter Tyserd3d9a502009-09-16 22:03:08 -050034#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk9c53f402003-10-15 23:53:47 +000035
wdenk13eb2212004-07-09 23:27:13 +000036/*
37 * sysclk for MPC85xx
38 *
39 * Two valid values are:
40 * 33000000
41 * 66000000
42 *
43 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk492b9e72004-08-01 23:02:45 +000044 * is likely the desired value here, so that is now the default.
45 * The board, however, can run at 66MHz. In any event, this value
46 * must match the settings of some switches. Details can be found
47 * in the README.mpc85xxads.
wdenk13eb2212004-07-09 23:27:13 +000048 */
49
wdenk492b9e72004-08-01 23:02:45 +000050#ifndef CONFIG_SYS_CLK_FREQ
51#define CONFIG_SYS_CLK_FREQ 33000000
wdenk9c53f402003-10-15 23:53:47 +000052#endif
53
wdenk13eb2212004-07-09 23:27:13 +000054/*
55 * These can be toggled for performance analysis, otherwise use default.
56 */
57#define CONFIG_L2_CACHE /* toggle L2 cache */
58#define CONFIG_BTB /* toggle branch predition */
wdenk13eb2212004-07-09 23:27:13 +000059
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
wdenk9c53f402003-10-15 23:53:47 +000061
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
63#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk9c53f402003-10-15 23:53:47 +000064
Timur Tabid8f341c2011-08-04 18:03:41 -050065#define CONFIG_SYS_CCSRBAR 0xe0000000
66#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk9c53f402003-10-15 23:53:47 +000067
Jon Loeliger99d50712008-03-18 11:12:44 -050068/* DDR Setup */
Jon Loeliger99d50712008-03-18 11:12:44 -050069#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
70#define CONFIG_DDR_SPD
71#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk492b9e72004-08-01 23:02:45 +000072
Jon Loeliger99d50712008-03-18 11:12:44 -050073#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
74
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
76#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk492b9e72004-08-01 23:02:45 +000077
Jon Loeliger99d50712008-03-18 11:12:44 -050078#define CONFIG_DIMM_SLOTS_PER_CTLR 1
79#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk492b9e72004-08-01 23:02:45 +000080
Jon Loeliger99d50712008-03-18 11:12:44 -050081/* I2C addresses of SPD EEPROMs */
82#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk492b9e72004-08-01 23:02:45 +000083
Jon Loeliger99d50712008-03-18 11:12:44 -050084/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
86#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
87#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
88#define CONFIG_SYS_DDR_TIMING_1 0x37344321
89#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
90#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
91#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
92#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk9c53f402003-10-15 23:53:47 +000093
wdenk13eb2212004-07-09 23:27:13 +000094/*
95 * SDRAM on the Local Bus
96 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020097#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
98#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk9c53f402003-10-15 23:53:47 +000099
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
101#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk9c53f402003-10-15 23:53:47 +0000102
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200103#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
104#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
105#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
106#undef CONFIG_SYS_FLASH_CHECKSUM
107#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
108#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk9c53f402003-10-15 23:53:47 +0000109
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200110#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk13eb2212004-07-09 23:27:13 +0000111
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
113#define CONFIG_SYS_RAMBOOT
wdenk9c53f402003-10-15 23:53:47 +0000114#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115#undef CONFIG_SYS_RAMBOOT
wdenk9c53f402003-10-15 23:53:47 +0000116#endif
117
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200118#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH_CFI
120#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk13eb2212004-07-09 23:27:13 +0000121
122#undef CONFIG_CLOCKS_IN_MHZ
wdenk9c53f402003-10-15 23:53:47 +0000123
wdenk13eb2212004-07-09 23:27:13 +0000124/*
125 * Local Bus Definitions
126 */
127
128/*
129 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk13eb2212004-07-09 23:27:13 +0000131 *
132 * For BR2, need:
133 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
134 * port-size = 32-bits = BR2[19:20] = 11
135 * no parity checking = BR2[21:22] = 00
136 * SDRAM for MSEL = BR2[24:26] = 011
137 * Valid = BR[31] = 1
138 *
139 * 0 4 8 12 16 20 24 28
140 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
141 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk13eb2212004-07-09 23:27:13 +0000143 * FIXME: the top 17 bits of BR2.
144 */
wdenk9c53f402003-10-15 23:53:47 +0000145
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk13eb2212004-07-09 23:27:13 +0000147
148/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk13eb2212004-07-09 23:27:13 +0000150 *
151 * For OR2, need:
152 * 64MB mask for AM, OR2[0:7] = 1111 1100
153 * XAM, OR2[17:18] = 11
154 * 9 columns OR2[19-21] = 010
155 * 13 rows OR2[23-25] = 100
156 * EAD set for extra time OR[31] = 1
157 *
158 * 0 4 8 12 16 20 24 28
159 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
160 */
161
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200162#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk13eb2212004-07-09 23:27:13 +0000163
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
165#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
166#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
167#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk13eb2212004-07-09 23:27:13 +0000168
Kumar Gala727c6a62009-03-26 01:34:38 -0500169#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
170 | LSDMR_RFCR5 \
171 | LSDMR_PRETOACT3 \
172 | LSDMR_ACTTORW3 \
173 | LSDMR_BL8 \
174 | LSDMR_WRC2 \
175 | LSDMR_CL3 \
176 | LSDMR_RFEN \
wdenk13eb2212004-07-09 23:27:13 +0000177 )
178
179/*
180 * SDRAM Controller configuration sequence.
181 */
Kumar Gala727c6a62009-03-26 01:34:38 -0500182#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
183#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
184#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
185#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
186#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk13eb2212004-07-09 23:27:13 +0000187
wdenk492b9e72004-08-01 23:02:45 +0000188/*
189 * 32KB, 8-bit wide for ADS config reg
190 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191#define CONFIG_SYS_BR4_PRELIM 0xf8000801
192#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
193#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk9c53f402003-10-15 23:53:47 +0000194
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_INIT_RAM_LOCK 1
196#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200197#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk9c53f402003-10-15 23:53:47 +0000198
Wolfgang Denk0191e472010-10-26 14:34:52 +0200199#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk9c53f402003-10-15 23:53:47 +0000201
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
203#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk9c53f402003-10-15 23:53:47 +0000204
205/* Serial Port */
wdenk13eb2212004-07-09 23:27:13 +0000206#define CONFIG_CONS_ON_SCC /* define if console on SCC */
207#undef CONFIG_CONS_NONE /* define if console on something else */
208#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
wdenk9c53f402003-10-15 23:53:47 +0000209
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk9c53f402003-10-15 23:53:47 +0000211 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
212
Jon Loeliger43d818f2006-10-20 15:50:15 -0500213/*
214 * I2C
215 */
Heiko Schocherf2850742012-10-24 13:48:22 +0200216#define CONFIG_SYS_I2C
217#define CONFIG_SYS_I2C_FSL
218#define CONFIG_SYS_FSL_I2C_SPEED 400000
219#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
220#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
221#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk9c53f402003-10-15 23:53:47 +0000222
wdenk13eb2212004-07-09 23:27:13 +0000223/* RapidIO MMU */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600224#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala3fe80872008-12-02 16:08:36 -0600225#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600226#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk9c53f402003-10-15 23:53:47 +0000228
wdenk13eb2212004-07-09 23:27:13 +0000229/*
230 * General PCI
Sergei Shtylyov6ffad932006-12-27 22:07:15 +0300231 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk13eb2212004-07-09 23:27:13 +0000232 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600233#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600234#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600235#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600237#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600238#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200239#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
240#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk13eb2212004-07-09 23:27:13 +0000241
242#if defined(CONFIG_PCI)
wdenk13eb2212004-07-09 23:27:13 +0000243#undef CONFIG_EEPRO100
wdenk9c53f402003-10-15 23:53:47 +0000244#undef CONFIG_TULIP
wdenk13eb2212004-07-09 23:27:13 +0000245
246#if !defined(CONFIG_PCI_PNP)
247 #define PCI_ENET0_IOADDR 0xe0000000
248 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denka1be4762008-05-20 16:00:29 +0200249 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk9c53f402003-10-15 23:53:47 +0000250#endif
wdenk13eb2212004-07-09 23:27:13 +0000251
252#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200253#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk13eb2212004-07-09 23:27:13 +0000254
255#endif /* CONFIG_PCI */
256
Andy Fleming8ed11962007-05-08 17:27:43 -0500257#ifdef CONFIG_TSEC_ENET
wdenk13eb2212004-07-09 23:27:13 +0000258
Andy Fleming8ed11962007-05-08 17:27:43 -0500259#ifndef CONFIG_MII
wdenk13eb2212004-07-09 23:27:13 +0000260#define CONFIG_MII 1 /* MII PHY management */
Andy Fleming8ed11962007-05-08 17:27:43 -0500261#endif
Kim Phillips177e58f2007-05-16 16:52:19 -0500262#define CONFIG_TSEC1 1
263#define CONFIG_TSEC1_NAME "TSEC0"
264#define CONFIG_TSEC2 1
265#define CONFIG_TSEC2_NAME "TSEC1"
wdenk13eb2212004-07-09 23:27:13 +0000266#define TSEC1_PHY_ADDR 0
267#define TSEC2_PHY_ADDR 1
268#define TSEC1_PHYIDX 0
269#define TSEC2_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500270#define TSEC1_FLAGS TSEC_GIGABIT
271#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500272
273/* Options are: TSEC[0-1] */
274#define CONFIG_ETHPRIME "TSEC0"
wdenk13eb2212004-07-09 23:27:13 +0000275
Andy Fleming8ed11962007-05-08 17:27:43 -0500276#endif /* CONFIG_TSEC_ENET */
277
Wolfgang Denka1be4762008-05-20 16:00:29 +0200278#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
wdenk13eb2212004-07-09 23:27:13 +0000279
Wolfgang Denka1be4762008-05-20 16:00:29 +0200280#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk13eb2212004-07-09 23:27:13 +0000281#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
282
283#if (CONFIG_ETHER_INDEX == 2)
wdenk9c53f402003-10-15 23:53:47 +0000284 /*
285 * - Rx-CLK is CLK13
286 * - Tx-CLK is CLK14
287 * - Select bus for bd/buffers
288 * - Full duplex
289 */
Mike Frysinger109de972011-10-17 05:38:58 +0000290 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
291 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200292 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
293 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk9c53f402003-10-15 23:53:47 +0000294 #define FETH2_RST 0x01
wdenk13eb2212004-07-09 23:27:13 +0000295#elif (CONFIG_ETHER_INDEX == 3)
wdenk9c53f402003-10-15 23:53:47 +0000296 /* need more definitions here for FE3 */
297 #define FETH3_RST 0x80
Wolfgang Denka1be4762008-05-20 16:00:29 +0200298#endif /* CONFIG_ETHER_INDEX */
wdenk13eb2212004-07-09 23:27:13 +0000299
Andy Fleming8ed11962007-05-08 17:27:43 -0500300#ifndef CONFIG_MII
301#define CONFIG_MII 1 /* MII PHY management */
302#endif
303
wdenk13eb2212004-07-09 23:27:13 +0000304#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
305
wdenk9c53f402003-10-15 23:53:47 +0000306/*
307 * GPIO pins used for bit-banged MII communications
308 */
309#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellini25e30722009-10-10 12:42:22 +0200310#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
311 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
312#define MDC_DECLARE MDIO_DECLARE
313
wdenk9c53f402003-10-15 23:53:47 +0000314#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
315#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
316#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
317
318#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
319 else iop->pdat &= ~0x00400000
320
321#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
322 else iop->pdat &= ~0x00200000
323
324#define MIIDELAY udelay(1)
wdenk13eb2212004-07-09 23:27:13 +0000325
wdenk9c53f402003-10-15 23:53:47 +0000326#endif
327
wdenk13eb2212004-07-09 23:27:13 +0000328/*
329 * Environment
330 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200331#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200332 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200333 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
334 #define CONFIG_ENV_SIZE 0x2000
wdenk9c53f402003-10-15 23:53:47 +0000335#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200336 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200337 #define CONFIG_ENV_SIZE 0x2000
wdenk9c53f402003-10-15 23:53:47 +0000338#endif
339
wdenk13eb2212004-07-09 23:27:13 +0000340#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200341#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk9c53f402003-10-15 23:53:47 +0000342
Jon Loeligere63319f2007-06-13 13:22:08 -0500343/*
Jon Loeligered26c742007-07-10 09:10:49 -0500344 * BOOTP options
345 */
346#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeligered26c742007-07-10 09:10:49 -0500347
wdenk13eb2212004-07-09 23:27:13 +0000348#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk9c53f402003-10-15 23:53:47 +0000349
350/*
351 * Miscellaneous configurable options
352 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200353#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
wdenk13eb2212004-07-09 23:27:13 +0000354
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200355#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk9c53f402003-10-15 23:53:47 +0000356
357/*
358 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500359 * have to be in the first 64 MB of memory, since this is
wdenk9c53f402003-10-15 23:53:47 +0000360 * the maximum mapped by the Linux kernel during initialization.
361 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500362#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
363#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk9c53f402003-10-15 23:53:47 +0000364
Jon Loeligere63319f2007-06-13 13:22:08 -0500365#if defined(CONFIG_CMD_KGDB)
wdenk9c53f402003-10-15 23:53:47 +0000366#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk9c53f402003-10-15 23:53:47 +0000367#endif
368
wdenk492b9e72004-08-01 23:02:45 +0000369/*
370 * Environment Configuration
371 */
wdenk9c53f402003-10-15 23:53:47 +0000372#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming458c3892007-08-16 16:35:02 -0500373#define CONFIG_HAS_ETH0
wdenk54070ab2004-12-31 09:32:47 +0000374#define CONFIG_HAS_ETH1
wdenk54070ab2004-12-31 09:32:47 +0000375#define CONFIG_HAS_ETH2
Kumar Galaf2982fa2007-11-28 22:40:31 -0600376#define CONFIG_HAS_ETH3
wdenk9c53f402003-10-15 23:53:47 +0000377#endif
378
wdenk13eb2212004-07-09 23:27:13 +0000379#define CONFIG_IPADDR 192.168.1.253
380
381#define CONFIG_HOSTNAME unknown
Joe Hershberger257ff782011-10-13 13:03:47 +0000382#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000383#define CONFIG_BOOTFILE "your.uImage"
wdenk13eb2212004-07-09 23:27:13 +0000384
385#define CONFIG_SERVERIP 192.168.1.1
386#define CONFIG_GATEWAYIP 192.168.1.1
387#define CONFIG_NETMASK 255.255.255.0
388
389#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
390
wdenk492b9e72004-08-01 23:02:45 +0000391#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Fleming29e484e2008-07-14 20:04:40 -0500392 "netdev=eth0\0" \
393 "consoledev=ttyCPM\0" \
394 "ramdiskaddr=1000000\0" \
395 "ramdiskfile=your.ramdisk.u-boot\0" \
396 "fdtaddr=400000\0" \
397 "fdtfile=mpc8560ads.dtb\0"
wdenk13eb2212004-07-09 23:27:13 +0000398
wdenk492b9e72004-08-01 23:02:45 +0000399#define CONFIG_NFSBOOTCOMMAND \
Andy Fleming29e484e2008-07-14 20:04:40 -0500400 "setenv bootargs root=/dev/nfs rw " \
401 "nfsroot=$serverip:$rootpath " \
402 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
403 "console=$consoledev,$baudrate $othbootargs;" \
404 "tftp $loadaddr $bootfile;" \
405 "tftp $fdtaddr $fdtfile;" \
406 "bootm $loadaddr - $fdtaddr"
wdenk13eb2212004-07-09 23:27:13 +0000407
408#define CONFIG_RAMBOOTCOMMAND \
Andy Fleming29e484e2008-07-14 20:04:40 -0500409 "setenv bootargs root=/dev/ram rw " \
410 "console=$consoledev,$baudrate $othbootargs;" \
411 "tftp $ramdiskaddr $ramdiskfile;" \
412 "tftp $loadaddr $bootfile;" \
413 "tftp $fdtaddr $fdtfile;" \
414 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk13eb2212004-07-09 23:27:13 +0000415
416#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk9c53f402003-10-15 23:53:47 +0000417
418#endif /* __CONFIG_H */