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TsiChung Liewf6afe722007-06-18 13:50:13 -05001/*
2 * Configuation settings for the Freescale MCF5329 FireEngine board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liewf6afe722007-06-18 13:50:13 -05008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5329EVB_H
15#define _M5329EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
TsiChung Liewf6afe722007-06-18 13:50:13 -050021
TsiChungLiewdb0022d2007-08-05 03:19:10 -050022#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020023#define CONFIG_SYS_UART_PORT (0)
TsiChung Liewf6afe722007-06-18 13:50:13 -050024
25#undef CONFIG_WATCHDOG
26#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
27
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020028#define CONFIG_SYS_UNIFY_CACHE
TsiChung Liewf6afe722007-06-18 13:50:13 -050029
30#define CONFIG_MCFFEC
31#ifdef CONFIG_MCFFEC
TsiChung Liewf6afe722007-06-18 13:50:13 -050032# define CONFIG_MII 1
TsiChung Liewb3162452008-03-30 01:22:13 -050033# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034# define CONFIG_SYS_DISCOVER_PHY
35# define CONFIG_SYS_RX_ETH_BUFFER 8
36# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liewf6afe722007-06-18 13:50:13 -050037
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038# define CONFIG_SYS_FEC0_PINMUX 0
39# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denka1be4762008-05-20 16:00:29 +020040# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
42# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChung Liewf6afe722007-06-18 13:50:13 -050043# define FECDUPLEX FULL
44# define FECSPEED _100BASET
45# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
47# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liewf6afe722007-06-18 13:50:13 -050048# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChung Liewf6afe722007-06-18 13:50:13 -050050#endif
51
TsiChung Liewf6afe722007-06-18 13:50:13 -050052#define CONFIG_MCFRTC
TsiChungLiew2e0aeef2007-07-05 22:39:07 -050053#undef RTC_DEBUG
TsiChung Liewf6afe722007-06-18 13:50:13 -050054
55/* Timer */
56#define CONFIG_MCFTMR
TsiChung Liewf6afe722007-06-18 13:50:13 -050057#undef CONFIG_MCFPIT
TsiChung Liewf6afe722007-06-18 13:50:13 -050058
TsiChungLiew876343b2007-08-05 04:11:20 -050059/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +020060#define CONFIG_SYS_I2C
61#define CONFIG_SYS_I2C_FSL
62#define CONFIG_SYS_FSL_I2C_SPEED 80000
63#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
64#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiew876343b2007-08-05 04:11:20 -050066
TsiChungLiewaedd3d72007-08-15 15:39:17 -050067#define CONFIG_UDP_CHECKSUM
68
TsiChung Liewf6afe722007-06-18 13:50:13 -050069#ifdef CONFIG_MCFFEC
TsiChungLiew876343b2007-08-05 04:11:20 -050070# define CONFIG_IPADDR 192.162.1.2
71# define CONFIG_NETMASK 255.255.255.0
72# define CONFIG_SERVERIP 192.162.1.1
TsiChung Liewf6afe722007-06-18 13:50:13 -050073# define CONFIG_GATEWAYIP 192.162.1.1
TsiChung Liewf6afe722007-06-18 13:50:13 -050074#endif /* FEC_ENET */
75
76#define CONFIG_HOSTNAME M5329EVB
77#define CONFIG_EXTRA_ENV_SETTINGS \
78 "netdev=eth0\0" \
79 "loadaddr=40010000\0" \
80 "u-boot=u-boot.bin\0" \
81 "load=tftp ${loadaddr) ${u-boot}\0" \
82 "upd=run load; run prog\0" \
Jason Jinded4eb42011-08-19 10:10:40 +080083 "prog=prot off 0 3ffff;" \
84 "era 0 3ffff;" \
TsiChung Liewf6afe722007-06-18 13:50:13 -050085 "cp.b ${loadaddr} 0 ${filesize};" \
86 "save\0" \
87 ""
88
TsiChungLiew876343b2007-08-05 04:11:20 -050089#define CONFIG_PRAM 512 /* 512 KB */
TsiChung Liewf6afe722007-06-18 13:50:13 -050090
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_LOAD_ADDR 0x40010000
TsiChung Liewf6afe722007-06-18 13:50:13 -050092
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#define CONFIG_SYS_CLK 80000000
94#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
TsiChung Liewf6afe722007-06-18 13:50:13 -050095
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_MBAR 0xFC000000
TsiChung Liewf6afe722007-06-18 13:50:13 -050097
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
TsiChungLiewec8468f2007-08-05 04:31:18 -050099
TsiChung Liewf6afe722007-06-18 13:50:13 -0500100/*
101 * Low Level Configuration Settings
102 * (address mappings, register initial values, etc.)
103 * You should know what you are doing if you make changes here.
104 */
105/*-----------------------------------------------------------------------
106 * Definitions for initial stack pointer and data area (in DPRAM)
107 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200109#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk0191e472010-10-26 14:34:52 +0200111#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChung Liewf6afe722007-06-18 13:50:13 -0500113
114/*-----------------------------------------------------------------------
115 * Start addresses for the final memory configuration
116 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liewf6afe722007-06-18 13:50:13 -0500118 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_SDRAM_BASE 0x40000000
120#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
121#define CONFIG_SYS_SDRAM_CFG1 0x53722730
122#define CONFIG_SYS_SDRAM_CFG2 0x56670000
123#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
124#define CONFIG_SYS_SDRAM_EMOD 0x40010000
125#define CONFIG_SYS_SDRAM_MODE 0x018D0000
TsiChung Liewf6afe722007-06-18 13:50:13 -0500126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
128#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500129
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
131#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
134#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500135
136/*
137 * For booting Linux, the board info and command line data
138 * have to be in the first 8 MB of memory, since this is
139 * the maximum mapped by the Linux kernel during initialization ??
140 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liew25a00632009-01-27 12:57:47 +0000142#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500143
144/*-----------------------------------------------------------------------
145 * FLASH organization
146 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_CFI
148#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200149# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
151# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
152# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
153# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
154# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500155#endif
156
stany MARCEL5ac9ea62011-10-19 00:17:13 +0800157#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158# define CONFIG_SYS_MAX_NAND_DEVICE 1
159# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
160# define CONFIG_SYS_NAND_SIZE 1
161# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
TsiChungLiewaedd3d72007-08-15 15:39:17 -0500162# define NAND_ALLOW_ERASE_ALL 1
163# define CONFIG_JFFS2_NAND 1
164# define CONFIG_JFFS2_DEV "nand0"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
TsiChungLiewaedd3d72007-08-15 15:39:17 -0500166# define CONFIG_JFFS2_PART_OFFSET 0x00000000
TsiChungLiewec8468f2007-08-05 04:31:18 -0500167#endif
168
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200169#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChung Liewf6afe722007-06-18 13:50:13 -0500170
171/* Configuration for environment
172 * Environment is embedded in u-boot in the second sector of the flash
173 */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200174#define CONFIG_ENV_OFFSET 0x4000
175#define CONFIG_ENV_SECT_SIZE 0x2000
TsiChung Liewf6afe722007-06-18 13:50:13 -0500176
angelo@sysam.it6312a952015-03-29 22:54:16 +0200177#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -0600178 . = DEFINED(env_offset) ? env_offset : .; \
179 env/embedded.o(.text*);
angelo@sysam.it6312a952015-03-29 22:54:16 +0200180
TsiChung Liewf6afe722007-06-18 13:50:13 -0500181/*-----------------------------------------------------------------------
182 * Cache Configuration
183 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liewf6afe722007-06-18 13:50:13 -0500185
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600186#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200187 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600188#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200189 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600190#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
191#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
192 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
193 CF_ACR_EN | CF_ACR_SM_ALL)
194#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
195 CF_CACR_DCM_P)
196
TsiChung Liewf6afe722007-06-18 13:50:13 -0500197/*-----------------------------------------------------------------------
198 * Chipselect bank definitions
199 */
200/*
201 * CS0 - NOR Flash 1, 2, 4, or 8MB
202 * CS1 - CompactFlash and registers
203 * CS2 - NAND Flash 16, 32, or 64MB
204 * CS3 - Available
205 * CS4 - Available
206 * CS5 - Available
207 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_CS0_BASE 0
209#define CONFIG_SYS_CS0_MASK 0x007f0001
210#define CONFIG_SYS_CS0_CTRL 0x00001fa0
TsiChung Liewf6afe722007-06-18 13:50:13 -0500211
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_CS1_BASE 0x10000000
213#define CONFIG_SYS_CS1_MASK 0x001f0001
214#define CONFIG_SYS_CS1_CTRL 0x002A3780
TsiChung Liewf6afe722007-06-18 13:50:13 -0500215
stany MARCEL5ac9ea62011-10-19 00:17:13 +0800216#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217#define CONFIG_SYS_CS2_BASE 0x20000000
stany MARCEL5ac9ea62011-10-19 00:17:13 +0800218#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219#define CONFIG_SYS_CS2_CTRL 0x00001f60
TsiChung Liewf6afe722007-06-18 13:50:13 -0500220#endif
221
TsiChung Liewf6afe722007-06-18 13:50:13 -0500222#endif /* _M5329EVB_H */