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Kever Yangec02b3c2017-02-23 15:37:51 +08001/*
2 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/arch/hardware.h>
9#include <asm/armv8/mmu.h>
10#include <asm/io.h>
11
Kever Yangc2053262017-06-23 16:11:11 +080012DECLARE_GLOBAL_DATA_PTR;
13
Kever Yangec02b3c2017-02-23 15:37:51 +080014static struct mm_region rk3328_mem_map[] = {
15 {
16 .virt = 0x0UL,
17 .phys = 0x0UL,
Kever Yang6cd0cab2017-06-13 21:00:12 +080018 .size = 0xff000000UL,
Kever Yangec02b3c2017-02-23 15:37:51 +080019 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
20 PTE_BLOCK_INNER_SHARE
21 }, {
Kever Yang6cd0cab2017-06-13 21:00:12 +080022 .virt = 0xff000000UL,
23 .phys = 0xff000000UL,
24 .size = 0x1000000UL,
Kever Yangec02b3c2017-02-23 15:37:51 +080025 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
26 PTE_BLOCK_NON_SHARE |
27 PTE_BLOCK_PXN | PTE_BLOCK_UXN
28 }, {
29 /* List terminator */
30 0,
31 }
32};
33
34struct mm_region *mem_map = rk3328_mem_map;
35
Kever Yangc2053262017-06-23 16:11:11 +080036int dram_init_banksize(void)
37{
38 size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
39
40 /* Reserve 0x200000 for ATF bl31 */
41 gd->bd->bi_dram[0].start = 0x200000;
42 gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
43
44 return 0;
45}
46
Kever Yangec02b3c2017-02-23 15:37:51 +080047int arch_cpu_init(void)
48{
49 /* We do some SoC one time setting here. */
50
51 return 0;
52}