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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02002/*
3 * (C) Copyright 2008
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 *
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003, Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
9 *
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020011 */
12
13#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -070014#include <clock_legacy.h>
Simon Glassdb229612019-08-01 09:46:42 -060015#include <env.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020016#include <pci.h>
Simon Glass8e201882020-05-10 11:39:54 -060017#include <uuid.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020018#include <asm/processor.h>
19#include <asm/immap_85xx.h>
20#include <ioports.h>
21#include <flash.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090022#include <linux/libfdt.h>
Sergei Poselenov09842c52008-05-07 15:10:49 +020023#include <fdt_support.h>
Andy Fleming7109ea32008-06-10 18:49:34 -050024#include <asm/io.h>
u-boot@bugs.denx.debbab0bc2008-09-11 15:40:01 +020025#include <i2c.h>
26#include <mb862xx.h>
27#include <video_fb.h>
Sergei Poselenov96dd16b2008-06-06 15:42:41 +020028#include "upm_table.h"
Detlev Zundel0244f672008-08-15 15:42:12 +020029
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020030DECLARE_GLOBAL_DATA_PTR;
31
32extern flash_info_t flash_info[]; /* FLASH chips info */
u-boot@bugs.denx.debbab0bc2008-09-11 15:40:01 +020033extern GraphicDevice mb862xx;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020034
35void local_bus_init (void);
36ulong flash_get_size (ulong base, int banknum);
37
38int checkboard (void)
39{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000041 char buf[64];
Sergei Poselenove13be1a2008-05-27 13:47:00 +020042 int f;
Simon Glass64b723f2017-08-03 12:22:12 -060043 int i = env_get_f("serial#", buf, sizeof(buf));
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000044#ifdef CONFIG_PCI
45 char *src;
46#endif
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020047
48 puts("Board: Socrates");
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000049 if (i > 0) {
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020050 puts(", serial# ");
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000051 puts(buf);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020052 }
53 putc('\n');
54
Heiko Schocher84cdae22019-10-16 05:55:54 +020055#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
Andy Fleming7109ea32008-06-10 18:49:34 -050056 /* Check the PCI_clk sel bit */
57 if (in_be32(&gur->porpllsr) & (1<<15)) {
Sergei Poselenove13be1a2008-05-27 13:47:00 +020058 src = "SYSCLK";
59 f = CONFIG_SYS_CLK_FREQ;
60 } else {
61 src = "PCI_CLK";
62 f = CONFIG_PCI_CLK_FREQ;
63 }
64 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020065#else
66 printf ("PCI1: disabled\n");
67#endif
68
69 /*
70 * Initialize local bus.
71 */
72 local_bus_init ();
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020073 return 0;
74}
75
76int misc_init_r (void)
77{
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020078 /*
79 * Adjust flash start and offset to detected values
80 */
81 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
82 gd->bd->bi_flashoffset = 0;
83
84 /*
85 * Check if boot FLASH isn't max size
86 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
Becky Bruce0d4cee12010-06-17 11:37:20 -050088 set_lbc_or(0, gd->bd->bi_flashstart |
89 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
90 set_lbc_br(0, gd->bd->bi_flashstart |
91 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020092
93 /*
94 * Re-check to get correct base address
95 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020097 }
98
99 /*
100 * Check if only one FLASH bank is available
101 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
Becky Bruce0d4cee12010-06-17 11:37:20 -0500103 set_lbc_or(1, 0);
104 set_lbc_br(1, 0);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200105
106 /*
107 * Re-do flash protection upon new addresses
108 */
Simon Glassc7443162020-05-10 11:39:53 -0600109 flash_protect(FLAG_PROTECT_CLEAR,
110 gd->bd->bi_flashstart, 0xffffffff,
111 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200112
113 /* Monitor protection ON by default */
Simon Glassc7443162020-05-10 11:39:53 -0600114 flash_protect(FLAG_PROTECT_SET,
115 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
116 monitor_flash_len - 1,
117 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200118
119 /* Environment protection ON by default */
Simon Glassc7443162020-05-10 11:39:53 -0600120 flash_protect(FLAG_PROTECT_SET,
121 CONFIG_ENV_ADDR,
122 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
123 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200124
125 /* Redundant environment protection ON by default */
Simon Glassc7443162020-05-10 11:39:53 -0600126 flash_protect(FLAG_PROTECT_SET,
127 CONFIG_ENV_ADDR_REDUND,
128 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200130 }
131
Heiko Schocher84cdae22019-10-16 05:55:54 +0200132#if defined(CONFIG_DM_PCI)
133 pci_init();
134#endif
135
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200136 return 0;
137}
138
139/*
140 * Initialize Local Bus
141 */
142void local_bus_init (void)
143{
Becky Bruce0d4cee12010-06-17 11:37:20 -0500144 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
Detlev Zundel0244f672008-08-15 15:42:12 +0200146 sys_info_t sysinfo;
147 uint clkdiv;
148 uint lbc_mhz;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149 uint lcrr = CONFIG_SYS_LBC_LCRR;
Detlev Zundel0244f672008-08-15 15:42:12 +0200150
151 get_sys_info (&sysinfo);
Trent Piepho1b560ac2008-12-03 15:16:34 -0800152 clkdiv = lbc->lcrr & LCRR_CLKDIV;
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530153 lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
Detlev Zundel0244f672008-08-15 15:42:12 +0200154
155 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
156 if (lbc_mhz >= 66)
157 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
158 else
159 lcrr |= LCRR_DBYP; /* DLL Bypass */
160
161 out_be32 (&lbc->lcrr, lcrr);
162 asm ("sync;isync;msync");
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200163
Detlev Zundel0244f672008-08-15 15:42:12 +0200164 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
165 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
166 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
167 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200168
Detlev Zundel0244f672008-08-15 15:42:12 +0200169 /* Init UPMA for FPGA access */
170 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
Simon Glass4be8fc92019-12-28 10:44:57 -0700171 upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200172
u-boot@bugs.denx.debbab0bc2008-09-11 15:40:01 +0200173 /* Init UPMB for Lime controller access */
174 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
Simon Glass4be8fc92019-12-28 10:44:57 -0700175 upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200176}
177
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200178#ifdef CONFIG_BOARD_EARLY_INIT_R
179int board_early_init_r (void)
180{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Detlev Zundel0244f672008-08-15 15:42:12 +0200182
183 /* set and reset the GPIO pin 2 which will reset the W83782G chip */
184 out_8((unsigned char*)&gur->gpoutdr, 0x3F );
185 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
186 udelay(200);
187 out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
188
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200189 return (0);
190}
191#endif /* CONFIG_BOARD_EARLY_INIT_R */
Sergei Poselenov09842c52008-05-07 15:10:49 +0200192
Robert P. J. Day3c757002016-05-19 15:23:12 -0400193#ifdef CONFIG_OF_BOARD_SETUP
Simon Glass2aec3cc2014-10-23 18:58:47 -0600194int ft_board_setup(void *blob, bd_t *bd)
Sergei Poselenov09842c52008-05-07 15:10:49 +0200195{
Detlev Zundel0244f672008-08-15 15:42:12 +0200196 u32 val[12];
197 int rc, i = 0;
Sergei Poselenov09842c52008-05-07 15:10:49 +0200198
199 ft_cpu_setup(blob, bd);
200
Detlev Zundel0244f672008-08-15 15:42:12 +0200201 /* Fixup NOR FLASH mapping */
202 val[i++] = 0; /* chip select number */
203 val[i++] = 0; /* always 0 */
204 val[i++] = gd->bd->bi_flashstart;
205 val[i++] = gd->bd->bi_flashsize;
Sergei Poselenov09842c52008-05-07 15:10:49 +0200206
Heiko Schocherff109932019-10-16 05:55:51 +0200207#if defined(CONFIG_VIDEO_MB862xx)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208 if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200209 /* Fixup LIME mapping */
210 val[i++] = 2; /* chip select number */
211 val[i++] = 0; /* always 0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212 val[i++] = CONFIG_SYS_LIME_BASE;
213 val[i++] = CONFIG_SYS_LIME_SIZE;
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200214 }
Heiko Schocherff109932019-10-16 05:55:51 +0200215#endif
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200216
Detlev Zundel0244f672008-08-15 15:42:12 +0200217 /* Fixup FPGA mapping */
218 val[i++] = 3; /* chip select number */
219 val[i++] = 0; /* always 0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220 val[i++] = CONFIG_SYS_FPGA_BASE;
221 val[i++] = CONFIG_SYS_FPGA_SIZE;
Sergei Poselenovbc3d08d2008-06-06 15:42:45 +0200222
Detlev Zundel0244f672008-08-15 15:42:12 +0200223 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
224 val, i * sizeof(u32), 1);
Sergei Poselenovbc3d08d2008-06-06 15:42:45 +0200225 if (rc)
Detlev Zundel0244f672008-08-15 15:42:12 +0200226 printf("Unable to update localbus ranges, err=%s\n",
Sergei Poselenovbc3d08d2008-06-06 15:42:45 +0200227 fdt_strerror(rc));
Simon Glass2aec3cc2014-10-23 18:58:47 -0600228
229 return 0;
Sergei Poselenov09842c52008-05-07 15:10:49 +0200230}
Robert P. J. Day3c757002016-05-19 15:23:12 -0400231#endif /* CONFIG_OF_BOARD_SETUP */
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200232
Heiko Schocher66daf322019-10-16 05:55:49 +0200233#if defined(CONFIG_OF_SEPARATE)
234void *board_fdt_blob_setup(void)
235{
236 void *fw_dtb;
237
238 fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
239 if (fdt_magic(fw_dtb) != FDT_MAGIC) {
240 printf("DTB is not passed via %x\n", (u32)fw_dtb);
241 return NULL;
242 }
243
244 return fw_dtb;
245}
246#endif
Heiko Schocher08ce3722019-10-16 05:55:53 +0200247
248int get_serial_clock(void)
249{
250 return 333333330;
251}