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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Reinhard Arlt46911792009-07-25 06:19:12 +02002/*
3 * vme8349.c -- esd VME8349 board support
4 *
5 * Copyright (c) 2008-2009 esd gmbh.
6 *
7 * (C) Copyright 2006
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
11 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
Reinhard Arlt46911792009-07-25 06:19:12 +020012 */
13
14#include <common.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -070015#include <fdt_support.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070016#include <init.h>
Reinhard Arlt46911792009-07-25 06:19:12 +020017#include <ioports.h>
18#include <mpc83xx.h>
19#include <asm/mpc8349_pci.h>
20#if defined(CONFIG_OF_LIBFDT)
Masahiro Yamada75f82d02018-03-05 01:20:11 +090021#include <linux/libfdt.h>
Reinhard Arlt46911792009-07-25 06:19:12 +020022#endif
23#include <asm/io.h>
24#include <asm/mmu.h>
Reinhard Arlt63881352009-12-08 09:13:08 +010025#include <spd.h>
26#include <spd_sdram.h>
27#include <i2c.h>
28#include <netdev.h>
Reinhard Arlt46911792009-07-25 06:19:12 +020029
Simon Glass39f90ba2017-03-31 08:40:25 -060030DECLARE_GLOBAL_DATA_PTR;
31
Reinhard Arlt46911792009-07-25 06:19:12 +020032void ddr_enable_ecc(unsigned int dram_size);
33
Simon Glassd35f3382017-04-06 12:47:05 -060034int dram_init(void)
Reinhard Arlt46911792009-07-25 06:19:12 +020035{
36 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
37 u32 msize = 0;
38
39 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
Simon Glass39f90ba2017-03-31 08:40:25 -060040 return -ENXIO;
Reinhard Arlt46911792009-07-25 06:19:12 +020041
Reinhard Arlt63881352009-12-08 09:13:08 +010042 /* DDR SDRAM - Main memory */
Mario Sixc9f92772019-01-21 09:18:15 +010043 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
Reinhard Arlt46911792009-07-25 06:19:12 +020044
Reinhard Arlt63881352009-12-08 09:13:08 +010045 msize = spd_sdram();
Reinhard Arlt46911792009-07-25 06:19:12 +020046
47#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
48 /*
49 * Initialize and enable DDR ECC.
50 */
51 ddr_enable_ecc(msize * 1024 * 1024);
52#endif
53
54 /* Now check memory size (after ECC is initialized) */
55 msize = get_ram_size(0, msize);
56
57 /* return total bus SDRAM size(bytes) -- DDR */
Simon Glass39f90ba2017-03-31 08:40:25 -060058 gd->ram_size = msize * 1024 * 1024;
59
60 return 0;
Reinhard Arlt46911792009-07-25 06:19:12 +020061}
62
63int checkboard(void)
64{
Mario Sixa83f5492019-01-21 09:17:38 +010065#ifdef CONFIG_TARGET_CADDY2
Reinhard Arlt63881352009-12-08 09:13:08 +010066 puts("Board: esd VME-CADDY/2\n");
67#else
68 puts("Board: esd VME-CPU/8349\n");
69#endif
Reinhard Arlt46911792009-07-25 06:19:12 +020070
71 return 0;
72}
Reinhard Arlt63881352009-12-08 09:13:08 +010073
Mario Sixa83f5492019-01-21 09:17:38 +010074#ifdef CONFIG_TARGET_CADDY2
Reinhard Arlt63881352009-12-08 09:13:08 +010075int board_eth_init(bd_t *bis)
76{
77 return pci_eth_init(bis);
78}
79#endif
Reinhard Arlt46911792009-07-25 06:19:12 +020080
81#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glass2aec3cc2014-10-23 18:58:47 -060082int ft_board_setup(void *blob, bd_t *bd)
Reinhard Arlt46911792009-07-25 06:19:12 +020083{
84 ft_cpu_setup(blob, bd);
Reinhard Arlt63881352009-12-08 09:13:08 +010085
Reinhard Arlt46911792009-07-25 06:19:12 +020086#ifdef CONFIG_PCI
87 ft_pci_setup(blob, bd);
88#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -060089
90 return 0;
Reinhard Arlt46911792009-07-25 06:19:12 +020091}
92#endif
Reinhard Arlt63881352009-12-08 09:13:08 +010093
94int misc_init_r()
95{
96 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
97
Becky Bruce0d4cee12010-06-17 11:37:20 -050098 clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
Reinhard Arlt63881352009-12-08 09:13:08 +010099
100 return 0;
101}
102
103/*
104 * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
105 * and VME-CADDY/2) have different SDRAM configurations.
106 */
Mario Sixa83f5492019-01-21 09:17:38 +0100107#ifdef CONFIG_TARGET_CADDY2
Reinhard Arlt63881352009-12-08 09:13:08 +0100108#define SMALL_RAM 0xff
109#define LARGE_RAM 0x00
110#else
111#define SMALL_RAM 0x00
112#define LARGE_RAM 0xff
113#endif
114
115#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
116
117static spd_eeprom_t default_spd_eeprom = {
118 SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
119 SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
120 SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
121 SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
122 SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
123 SPD_VAL(0x00, 0x00), /* 05 */
124 SPD_VAL(0x40, 0x40), /* 06 */
125 SPD_VAL(0x00, 0x00), /* 07 */
126 SPD_VAL(0x05, 0x05), /* 08 */
127 SPD_VAL(0x30, 0x30), /* 09 */
128 SPD_VAL(0x45, 0x45), /* 10 */
129 SPD_VAL(0x02, 0x02), /* 11 ecc used */
130 SPD_VAL(0x82, 0x82), /* 12 */
131 SPD_VAL(0x10, 0x10), /* 13 */
132 SPD_VAL(0x08, 0x08), /* 14 */
133 SPD_VAL(0x00, 0x00), /* 15 */
134 SPD_VAL(0x0c, 0x0c), /* 16 */
135 SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
136 SPD_VAL(0x38, 0x38), /* 18 */
137 SPD_VAL(0x00, 0x00), /* 19 */
138 SPD_VAL(0x02, 0x02), /* 20 */
139 SPD_VAL(0x00, 0x00), /* 21 */
140 SPD_VAL(0x03, 0x03), /* 22 */
141 SPD_VAL(0x3d, 0x3d), /* 23 */
142 SPD_VAL(0x45, 0x45), /* 24 */
143 SPD_VAL(0x50, 0x50), /* 25 */
144 SPD_VAL(0x45, 0x45), /* 26 */
145 SPD_VAL(0x3c, 0x3c), /* 27 */
146 SPD_VAL(0x28, 0x28), /* 28 */
147 SPD_VAL(0x3c, 0x3c), /* 29 */
148 SPD_VAL(0x2d, 0x2d), /* 30 */
149 SPD_VAL(0x20, 0x80), /* 31 */
150 SPD_VAL(0x20, 0x20), /* 32 */
151 SPD_VAL(0x27, 0x27), /* 33 */
152 SPD_VAL(0x10, 0x10), /* 34 */
153 SPD_VAL(0x17, 0x17), /* 35 */
154 SPD_VAL(0x3c, 0x3c), /* 36 */
155 SPD_VAL(0x1e, 0x1e), /* 37 */
156 SPD_VAL(0x1e, 0x1e), /* 38 */
157 SPD_VAL(0x00, 0x00), /* 39 */
158 SPD_VAL(0x00, 0x06), /* 40 */
159 SPD_VAL(0x37, 0x37), /* 41 */
160 SPD_VAL(0x4b, 0x7f), /* 42 */
161 SPD_VAL(0x80, 0x80), /* 43 */
162 SPD_VAL(0x18, 0x18), /* 44 */
163 SPD_VAL(0x22, 0x22), /* 45 */
164 SPD_VAL(0x00, 0x00), /* 46 */
165 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
166 SPD_VAL(0x10, 0x10), /* 62 */
167 SPD_VAL(0x7e, 0x1d), /* 63 */
168 { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
169 SPD_VAL(0x00, 0x00), /* 72 */
Mario Sixa83f5492019-01-21 09:17:38 +0100170#ifdef CONFIG_TARGET_CADDY2
Reinhard Arlt63881352009-12-08 09:13:08 +0100171 { "vme-caddy/2 ram " }
172#else
173 { "vme-cpu/2 ram " }
174#endif
175};
176
177int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
178{
Heiko Schocherf2850742012-10-24 13:48:22 +0200179 int old_bus = i2c_get_bus_num();
Reinhard Arlt63881352009-12-08 09:13:08 +0100180 unsigned int l, sum;
181 int valid = 0;
182
Heiko Schocherf2850742012-10-24 13:48:22 +0200183 i2c_set_bus_num(0);
Reinhard Arlt63881352009-12-08 09:13:08 +0100184
185 if (i2c_read(chip, addr, alen, buffer, len) == 0)
186 if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
187 sum = 0;
188 for (l = 0; l < 63; l++)
189 sum = (sum + buffer[l]) & 0xff;
190 if (sum == buffer[63])
191 valid = 1;
192 else
193 printf("Invalid checksum in EEPROM %02x %02x\n",
194 sum, buffer[63]);
195 }
196
197 if (valid == 0) {
198 memcpy(buffer, (void *)&default_spd_eeprom, len);
199 sum = 0;
200 for (l = 0; l < 63; l++)
201 sum = (sum + buffer[l]) & 0xff;
202 if (sum != buffer[63])
203 printf("Invalid checksum in FLASH %02x %02x\n",
204 sum, buffer[63]);
205 buffer[63] = sum;
206 }
207
Heiko Schocherf2850742012-10-24 13:48:22 +0200208 i2c_set_bus_num(old_bus);
Reinhard Arlt63881352009-12-08 09:13:08 +0100209
210 return 0;
211}