blob: 2d58b3b268b1df7abca510474a74eebe612f98ac [file] [log] [blame]
Shaohui Xiedd335672015-11-11 17:58:37 +08001/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1043AQDS_H__
8#define __LS1043AQDS_H__
9
10#include "ls1043a_common.h"
11
Shaohui Xiedd335672015-11-11 17:58:37 +080012#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
13#define CONFIG_SYS_TEXT_BASE 0x82000000
Qianyu Gong138a36a2016-01-25 15:16:07 +080014#elif defined(CONFIG_QSPI_BOOT)
Alison Wangb5b8bfa2017-05-16 10:45:58 +080015#define CONFIG_SYS_TEXT_BASE 0x40100000
Shaohui Xiedd335672015-11-11 17:58:37 +080016#else
17#define CONFIG_SYS_TEXT_BASE 0x60100000
18#endif
19
20#ifndef __ASSEMBLY__
21unsigned long get_board_sys_clk(void);
22unsigned long get_board_ddr_clk(void);
23#endif
24
Qianyu Gonga92f2132016-06-13 11:20:31 +080025#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
26#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Shaohui Xiedd335672015-11-11 17:58:37 +080027
28#define CONFIG_SKIP_LOWLEVEL_INIT
29
30#define CONFIG_LAYERSCAPE_NS_ACCESS
31
32#define CONFIG_DIMM_SLOTS_PER_CTLR 1
33/* Physical Memory Map */
34#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Shaohui Xie16f15fa2016-01-04 11:03:44 +080035#define CONFIG_NR_DRAM_BANKS 2
Shaohui Xiedd335672015-11-11 17:58:37 +080036
37#define CONFIG_DDR_SPD
38#define SPD_EEPROM_ADDRESS 0x51
39#define CONFIG_SYS_SPD_BUS_NUM 0
40
Hou Zhiqianga43c3ac2017-02-06 11:29:00 +080041#ifndef CONFIG_SPL
Shaohui Xiedd335672015-11-11 17:58:37 +080042#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
Hou Zhiqianga43c3ac2017-02-06 11:29:00 +080043#endif
Shaohui Xiedd335672015-11-11 17:58:37 +080044
45#define CONFIG_DDR_ECC
46#ifdef CONFIG_DDR_ECC
47#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
49#endif
50
Shaohui Xiedd335672015-11-11 17:58:37 +080051#ifdef CONFIG_SYS_DPAA_FMAN
52#define CONFIG_FMAN_ENET
53#define CONFIG_PHYLIB
54#define CONFIG_PHY_VITESSE
55#define CONFIG_PHY_REALTEK
56#define CONFIG_PHYLIB_10G
57#define RGMII_PHY1_ADDR 0x1
58#define RGMII_PHY2_ADDR 0x2
59#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
60#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
61#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
62#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
63/* PHY address on QSGMII riser card on slot 1 */
64#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
65#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
66#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
67#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
68/* PHY address on QSGMII riser card on slot 2 */
69#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
70#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
71#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
72#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
73#endif
74
75#ifdef CONFIG_RAMBOOT_PBL
76#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
77#endif
78
79#ifdef CONFIG_NAND_BOOT
80#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
81#endif
82
83#ifdef CONFIG_SD_BOOT
Gong Qianyu760df892016-01-25 15:16:06 +080084#ifdef CONFIG_SD_BOOT_QSPI
85#define CONFIG_SYS_FSL_PBL_RCW \
86 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
87#else
Shaohui Xiedd335672015-11-11 17:58:37 +080088#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
89#endif
Gong Qianyu760df892016-01-25 15:16:06 +080090#endif
Shaohui Xiedd335672015-11-11 17:58:37 +080091
Wenbin Song7e6b49e2016-01-21 17:14:55 +080092/* LPUART */
93#ifdef CONFIG_LPUART
94#define CONFIG_LPUART_32B_REG
95#endif
96
Tang Yuantian57894be2015-12-09 15:32:18 +080097/* SATA */
98#define CONFIG_LIBATA
99#define CONFIG_SCSI_AHCI
100#define CONFIG_SCSI_AHCI_PLAT
Tang Yuantian57894be2015-12-09 15:32:18 +0800101
Wenbin Song63b11da2016-03-09 13:38:25 +0800102/* EEPROM */
103#define CONFIG_ID_EEPROM
104#define CONFIG_SYS_I2C_EEPROM_NXID
105#define CONFIG_SYS_EEPROM_BUS_NUM 0
106#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
107#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
108#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
109#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
110
Tang Yuantian57894be2015-12-09 15:32:18 +0800111#define CONFIG_SYS_SATA AHCI_BASE_ADDR
112
113#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
114#define CONFIG_SYS_SCSI_MAX_LUN 1
115#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
116 CONFIG_SYS_SCSI_MAX_LUN)
117
Shaohui Xiedd335672015-11-11 17:58:37 +0800118/*
119 * IFC Definitions
120 */
Qianyu Gong138a36a2016-01-25 15:16:07 +0800121#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Shaohui Xiedd335672015-11-11 17:58:37 +0800122#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
123#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
124 CSPR_PORT_SIZE_16 | \
125 CSPR_MSEL_NOR | \
126 CSPR_V)
127#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
128#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
129 + 0x8000000) | \
130 CSPR_PORT_SIZE_16 | \
131 CSPR_MSEL_NOR | \
132 CSPR_V)
133#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
134
135#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
136 CSOR_NOR_TRHZ_80)
137#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
138 FTIM0_NOR_TEADC(0x5) | \
139 FTIM0_NOR_TEAHC(0x5))
140#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
141 FTIM1_NOR_TRAD_NOR(0x1a) | \
142 FTIM1_NOR_TSEQRAD_NOR(0x13))
143#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
144 FTIM2_NOR_TCH(0x4) | \
145 FTIM2_NOR_TWPH(0xe) | \
146 FTIM2_NOR_TWP(0x1c))
147#define CONFIG_SYS_NOR_FTIM3 0
148
Wenbin Song810a91b2016-04-01 17:28:41 +0800149#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Shaohui Xiedd335672015-11-11 17:58:37 +0800150#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
151#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
152#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
153
154#define CONFIG_SYS_FLASH_EMPTY_INFO
155#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
156 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
157
158#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
159#define CONFIG_SYS_WRITE_SWAPPED_DATA
160
161/*
162 * NAND Flash Definitions
163 */
164#define CONFIG_NAND_FSL_IFC
165
166#define CONFIG_SYS_NAND_BASE 0x7e800000
167#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
168
169#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
170
171#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
172 | CSPR_PORT_SIZE_8 \
173 | CSPR_MSEL_NAND \
174 | CSPR_V)
175#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
176#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
177 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
178 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
179 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
180 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
181 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
182 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
183
184#define CONFIG_SYS_NAND_ONFI_DETECTION
185
186#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
187 FTIM0_NAND_TWP(0x18) | \
188 FTIM0_NAND_TWCHT(0x7) | \
189 FTIM0_NAND_TWH(0xa))
190#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
191 FTIM1_NAND_TWBE(0x39) | \
192 FTIM1_NAND_TRR(0xe) | \
193 FTIM1_NAND_TRP(0x18))
194#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
195 FTIM2_NAND_TREH(0xa) | \
196 FTIM2_NAND_TWHRE(0x1e))
197#define CONFIG_SYS_NAND_FTIM3 0x0
198
199#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
200#define CONFIG_SYS_MAX_NAND_DEVICE 1
201#define CONFIG_MTD_NAND_VERIFY_WRITE
Shaohui Xiedd335672015-11-11 17:58:37 +0800202
203#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Gong Qianyu760df892016-01-25 15:16:06 +0800204#endif
Shaohui Xiedd335672015-11-11 17:58:37 +0800205
206#ifdef CONFIG_NAND_BOOT
207#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
208#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
209#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
210#endif
211
Qianyu Gong138a36a2016-01-25 15:16:07 +0800212#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyu760df892016-01-25 15:16:06 +0800213#define CONFIG_QIXIS_I2C_ACCESS
Qianyu Gonga92f2132016-06-13 11:20:31 +0800214#define CONFIG_SYS_I2C_EARLY_INIT
Gong Qianyu760df892016-01-25 15:16:06 +0800215#endif
216
Shaohui Xiedd335672015-11-11 17:58:37 +0800217/*
218 * QIXIS Definitions
219 */
220#define CONFIG_FSL_QIXIS
221
222#ifdef CONFIG_FSL_QIXIS
223#define QIXIS_BASE 0x7fb00000
224#define QIXIS_BASE_PHYS QIXIS_BASE
225#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
226#define QIXIS_LBMAP_SWITCH 6
227#define QIXIS_LBMAP_MASK 0x0f
228#define QIXIS_LBMAP_SHIFT 0
229#define QIXIS_LBMAP_DFLTBANK 0x00
230#define QIXIS_LBMAP_ALTBANK 0x04
Gong Qianyu9da2c672015-12-31 18:29:04 +0800231#define QIXIS_LBMAP_NAND 0x09
232#define QIXIS_LBMAP_SD 0x00
Gong Qianyu760df892016-01-25 15:16:06 +0800233#define QIXIS_LBMAP_SD_QSPI 0xff
Qianyu Gong138a36a2016-01-25 15:16:07 +0800234#define QIXIS_LBMAP_QSPI 0xff
Gong Qianyu9da2c672015-12-31 18:29:04 +0800235#define QIXIS_RCW_SRC_NAND 0x106
236#define QIXIS_RCW_SRC_SD 0x040
Qianyu Gong138a36a2016-01-25 15:16:07 +0800237#define QIXIS_RCW_SRC_QSPI 0x045
Gong Qianyu4ce7be02015-12-31 18:29:03 +0800238#define QIXIS_RST_CTL_RESET 0x41
Shaohui Xiedd335672015-11-11 17:58:37 +0800239#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
240#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
241#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
242
243#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
244#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
245 CSPR_PORT_SIZE_8 | \
246 CSPR_MSEL_GPCM | \
247 CSPR_V)
248#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
249#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
250 CSOR_NOR_NOR_MODE_AVD_NOR | \
251 CSOR_NOR_TRHZ_80)
252
253/*
254 * QIXIS Timing parameters for IFC GPCM
255 */
256#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
257 FTIM0_GPCM_TEADC(0x20) | \
258 FTIM0_GPCM_TEAHC(0x10))
259#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
260 FTIM1_GPCM_TRAD(0x1f))
261#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
262 FTIM2_GPCM_TCH(0x8) | \
263 FTIM2_GPCM_TWP(0xf0))
264#define CONFIG_SYS_FPGA_FTIM3 0x0
265#endif
266
267#ifdef CONFIG_NAND_BOOT
268#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
269#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
270#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
271#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
272#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
273#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
274#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
275#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
276#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
277#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
278#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
279#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
280#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
281#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
282#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
283#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
284#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
285#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
286#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
287#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
288#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
289#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
290#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
291#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
292#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
293#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
294#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
295#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
296#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
297#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
298#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
299#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
300#else
301#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
302#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
303#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
304#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
305#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
306#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
307#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
308#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
309#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
310#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
311#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
312#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
313#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
314#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
315#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
316#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
317#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
318#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
319#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
320#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
321#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
322#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
323#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
324#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
325#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
326#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
327#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
328#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
329#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
330#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
331#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
332#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
333#endif
334
335/*
336 * I2C bus multiplexer
337 */
338#define I2C_MUX_PCA_ADDR_PRI 0x77
339#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
340#define I2C_RETIMER_ADDR 0x18
341#define I2C_MUX_CH_DEFAULT 0x8
342#define I2C_MUX_CH_CH7301 0xC
343#define I2C_MUX_CH5 0xD
344#define I2C_MUX_CH7 0xF
345
346#define I2C_MUX_CH_VOL_MONITOR 0xa
347
348/* Voltage monitor on channel 2*/
349#define I2C_VOL_MONITOR_ADDR 0x40
350#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
351#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
352#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
353
354#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
355#ifndef CONFIG_SPL_BUILD
356#define CONFIG_VID
357#endif
358#define CONFIG_VOL_MONITOR_IR36021_SET
359#define CONFIG_VOL_MONITOR_INA220
360/* The lowest and highest voltage allowed for LS1043AQDS */
361#define VDD_MV_MIN 819
362#define VDD_MV_MAX 1212
363
Gong Qianyu760df892016-01-25 15:16:06 +0800364/* QSPI device */
Qianyu Gong138a36a2016-01-25 15:16:07 +0800365#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyu760df892016-01-25 15:16:06 +0800366#define CONFIG_FSL_QSPI
367#ifdef CONFIG_FSL_QSPI
368#define CONFIG_SPI_FLASH_SPANSION
369#define FSL_QSPI_FLASH_SIZE (1 << 24)
370#define FSL_QSPI_FLASH_NUM 2
371#endif
372#endif
373
Qianyu Gong8d3d5c42016-02-16 13:12:53 +0800374/* USB */
375#define CONFIG_HAS_FSL_XHCI_USB
376#ifdef CONFIG_HAS_FSL_XHCI_USB
Qianyu Gong8d3d5c42016-02-16 13:12:53 +0800377#define CONFIG_USB_XHCI_FSL
Qianyu Gong8d3d5c42016-02-16 13:12:53 +0800378#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
Qianyu Gong8d3d5c42016-02-16 13:12:53 +0800379#endif
380
Shaohui Xiedd335672015-11-11 17:58:37 +0800381/*
382 * Miscellaneous configurable options
383 */
384#define CONFIG_MISC_INIT_R
385#define CONFIG_SYS_LONGHELP /* undef to save memory */
Shaohui Xiedd335672015-11-11 17:58:37 +0800386#define CONFIG_AUTO_COMPLETE
387#define CONFIG_SYS_PBSIZE \
388 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
389#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
390
Shaohui Xiedd335672015-11-11 17:58:37 +0800391#define CONFIG_SYS_MEMTEST_START 0x80000000
392#define CONFIG_SYS_MEMTEST_END 0x9fffffff
393
394#define CONFIG_SYS_HZ 1000
395
Shaohui Xiedd335672015-11-11 17:58:37 +0800396#define CONFIG_SYS_INIT_SP_OFFSET \
397 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
398
399#ifdef CONFIG_SPL_BUILD
400#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
401#else
402#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
403#endif
404
405/*
406 * Environment
407 */
408#define CONFIG_ENV_OVERWRITE
409
410#ifdef CONFIG_NAND_BOOT
Shaohui Xiedd335672015-11-11 17:58:37 +0800411#define CONFIG_ENV_SIZE 0x2000
Alison Wangb5b8bfa2017-05-16 10:45:58 +0800412#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shaohui Xiedd335672015-11-11 17:58:37 +0800413#elif defined(CONFIG_SD_BOOT)
Alison Wangb5b8bfa2017-05-16 10:45:58 +0800414#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
Shaohui Xiedd335672015-11-11 17:58:37 +0800415#define CONFIG_SYS_MMC_ENV_DEV 0
416#define CONFIG_ENV_SIZE 0x2000
Qianyu Gong138a36a2016-01-25 15:16:07 +0800417#elif defined(CONFIG_QSPI_BOOT)
Qianyu Gong138a36a2016-01-25 15:16:07 +0800418#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
Alison Wangb5b8bfa2017-05-16 10:45:58 +0800419#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
Qianyu Gong138a36a2016-01-25 15:16:07 +0800420#define CONFIG_ENV_SECT_SIZE 0x10000
Shaohui Xiedd335672015-11-11 17:58:37 +0800421#else
Alison Wangb5b8bfa2017-05-16 10:45:58 +0800422#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
Shaohui Xiedd335672015-11-11 17:58:37 +0800423#define CONFIG_ENV_SECT_SIZE 0x20000
424#define CONFIG_ENV_SIZE 0x20000
425#endif
426
Shaohui Xiedd335672015-11-11 17:58:37 +0800427#define CONFIG_CMDLINE_TAG
428
Aneesh Bansal962021a2016-01-22 16:37:22 +0530429#include <asm/fsl_secure_boot.h>
430
Shaohui Xiedd335672015-11-11 17:58:37 +0800431#endif /* __LS1043AQDS_H__ */