Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * T1024/T1023 QDS board configuration file |
| 9 | */ |
| 10 | |
| 11 | #ifndef __T1024QDS_H |
| 12 | #define __T1024QDS_H |
| 13 | |
| 14 | /* High Level Configuration Options */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 15 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
| 16 | #define CONFIG_MP /* support multiple processors */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 17 | #define CONFIG_ENABLE_36BIT_PHYS |
| 18 | |
| 19 | #ifdef CONFIG_PHYS_64BIT |
| 20 | #define CONFIG_ADDR_MAP 1 |
| 21 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ |
| 22 | #endif |
| 23 | |
| 24 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 25 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 26 | |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 27 | #define CONFIG_ENV_OVERWRITE |
| 28 | |
| 29 | #define CONFIG_DEEP_SLEEP |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 30 | |
| 31 | #ifdef CONFIG_RAMBOOT_PBL |
| 32 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 33 | #define CONFIG_SPL_FLUSH_IMAGE |
| 34 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 35 | #define CONFIG_SYS_TEXT_BASE 0x00201000 |
| 36 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 |
| 37 | #define CONFIG_SPL_PAD_TO 0x40000 |
| 38 | #define CONFIG_SPL_MAX_SIZE 0x28000 |
| 39 | #define RESET_VECTOR_OFFSET 0x27FFC |
| 40 | #define BOOT_PAGE_OFFSET 0x27000 |
| 41 | #ifdef CONFIG_SPL_BUILD |
| 42 | #define CONFIG_SPL_SKIP_RELOCATE |
| 43 | #define CONFIG_SPL_COMMON_INIT_DDR |
| 44 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 45 | #endif |
| 46 | |
| 47 | #ifdef CONFIG_NAND |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 48 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
| 49 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 |
| 50 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 |
| 51 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) |
| 52 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 53 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 54 | #define CONFIG_SPL_NAND_BOOT |
| 55 | #endif |
| 56 | |
| 57 | #ifdef CONFIG_SPIFLASH |
| 58 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 59 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 60 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
| 61 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) |
| 62 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) |
| 63 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) |
| 64 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" |
| 65 | #ifndef CONFIG_SPL_BUILD |
| 66 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 67 | #endif |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 68 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 69 | #define CONFIG_SPL_SPI_BOOT |
| 70 | #endif |
| 71 | |
| 72 | #ifdef CONFIG_SDCARD |
| 73 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 74 | #define CONFIG_SPL_MMC_MINIMAL |
| 75 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| 76 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) |
| 77 | #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) |
| 78 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
| 79 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" |
| 80 | #ifndef CONFIG_SPL_BUILD |
| 81 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 82 | #endif |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 83 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 84 | #define CONFIG_SPL_MMC_BOOT |
| 85 | #endif |
| 86 | |
| 87 | #endif /* CONFIG_RAMBOOT_PBL */ |
| 88 | |
| 89 | #ifndef CONFIG_SYS_TEXT_BASE |
| 90 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
| 91 | #endif |
| 92 | |
| 93 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 94 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 95 | #endif |
| 96 | |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 97 | #ifdef CONFIG_MTD_NOR_FLASH |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 98 | #define CONFIG_FLASH_CFI_DRIVER |
| 99 | #define CONFIG_SYS_FLASH_CFI |
| 100 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 101 | #endif |
| 102 | |
| 103 | /* PCIe Boot - Master */ |
| 104 | #define CONFIG_SRIO_PCIE_BOOT_MASTER |
| 105 | /* |
| 106 | * for slave u-boot IMAGE instored in master memory space, |
| 107 | * PHYS must be aligned based on the SIZE |
| 108 | */ |
| 109 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull |
| 110 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ |
| 111 | #ifdef CONFIG_PHYS_64BIT |
| 112 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
| 113 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull |
| 114 | #else |
| 115 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 |
| 116 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 |
| 117 | #endif |
| 118 | /* |
| 119 | * for slave UCODE and ENV instored in master memory space, |
| 120 | * PHYS must be aligned based on the SIZE |
| 121 | */ |
| 122 | #ifdef CONFIG_PHYS_64BIT |
| 123 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
| 124 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
| 125 | #else |
| 126 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 |
| 127 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 |
| 128 | #endif |
| 129 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ |
| 130 | /* slave core release by master*/ |
| 131 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 |
| 132 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ |
| 133 | |
| 134 | /* PCIe Boot - Slave */ |
| 135 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
| 136 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 |
| 137 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ |
| 138 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) |
| 139 | /* Set 1M boot space for PCIe boot */ |
| 140 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) |
| 141 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ |
| 142 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) |
| 143 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 144 | #endif |
| 145 | |
| 146 | #if defined(CONFIG_SPIFLASH) |
| 147 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 148 | #define CONFIG_ENV_SPI_BUS 0 |
| 149 | #define CONFIG_ENV_SPI_CS 0 |
| 150 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 |
| 151 | #define CONFIG_ENV_SPI_MODE 0 |
| 152 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 153 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
| 154 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 155 | #elif defined(CONFIG_SDCARD) |
| 156 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 157 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 158 | #define CONFIG_ENV_SIZE 0x2000 |
| 159 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
| 160 | #elif defined(CONFIG_NAND) |
| 161 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 162 | #define CONFIG_ENV_SIZE 0x2000 |
| 163 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 164 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 165 | #define CONFIG_ENV_ADDR 0xffe20000 |
| 166 | #define CONFIG_ENV_SIZE 0x2000 |
| 167 | #elif defined(CONFIG_ENV_IS_NOWHERE) |
| 168 | #define CONFIG_ENV_SIZE 0x2000 |
| 169 | #else |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 170 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 171 | #define CONFIG_ENV_SIZE 0x2000 |
| 172 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
| 173 | #endif |
| 174 | |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 175 | #ifndef __ASSEMBLY__ |
| 176 | unsigned long get_board_sys_clk(void); |
| 177 | unsigned long get_board_ddr_clk(void); |
| 178 | #endif |
| 179 | |
| 180 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
| 181 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
| 182 | |
| 183 | /* |
| 184 | * These can be toggled for performance analysis, otherwise use default. |
| 185 | */ |
| 186 | #define CONFIG_SYS_CACHE_STASHING |
| 187 | #define CONFIG_BACKSIDE_L2_CACHE |
| 188 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E |
| 189 | #define CONFIG_BTB /* toggle branch predition */ |
| 190 | #define CONFIG_DDR_ECC |
| 191 | #ifdef CONFIG_DDR_ECC |
| 192 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 193 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 194 | #endif |
| 195 | |
| 196 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 197 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
| 198 | #define CONFIG_SYS_ALT_MEMTEST |
| 199 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 200 | |
| 201 | /* |
| 202 | * Config the L3 Cache as L3 SRAM |
| 203 | */ |
| 204 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
| 205 | #define CONFIG_SYS_L3_SIZE (256 << 10) |
| 206 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) |
| 207 | #ifdef CONFIG_RAMBOOT_PBL |
| 208 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) |
| 209 | #endif |
| 210 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) |
| 211 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) |
| 212 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) |
| 213 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) |
| 214 | |
| 215 | #ifdef CONFIG_PHYS_64BIT |
| 216 | #define CONFIG_SYS_DCSRBAR 0xf0000000 |
| 217 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull |
| 218 | #endif |
| 219 | |
| 220 | /* EEPROM */ |
| 221 | #define CONFIG_ID_EEPROM |
| 222 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 223 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 224 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 225 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 226 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 227 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
| 228 | |
| 229 | /* |
| 230 | * DDR Setup |
| 231 | */ |
| 232 | #define CONFIG_VERY_BIG_RAM |
| 233 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 234 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 235 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 236 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 237 | #define CONFIG_DDR_SPD |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 238 | |
| 239 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 240 | #define SPD_EEPROM_ADDRESS 0x51 |
| 241 | |
| 242 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
| 243 | |
| 244 | /* |
| 245 | * IFC Definitions |
| 246 | */ |
| 247 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 |
| 248 | #ifdef CONFIG_PHYS_64BIT |
| 249 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
| 250 | #else |
| 251 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 252 | #endif |
| 253 | |
| 254 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) |
| 255 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ |
| 256 | + 0x8000000) | \ |
| 257 | CSPR_PORT_SIZE_16 | \ |
| 258 | CSPR_MSEL_NOR | \ |
| 259 | CSPR_V) |
| 260 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) |
| 261 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
| 262 | CSPR_PORT_SIZE_16 | \ |
| 263 | CSPR_MSEL_NOR | \ |
| 264 | CSPR_V) |
| 265 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
| 266 | /* NOR Flash Timing Params */ |
| 267 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
| 268 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
| 269 | FTIM0_NOR_TEADC(0x5) | \ |
| 270 | FTIM0_NOR_TEAHC(0x5)) |
| 271 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
| 272 | FTIM1_NOR_TRAD_NOR(0x1A) |\ |
| 273 | FTIM1_NOR_TSEQRAD_NOR(0x13)) |
| 274 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
| 275 | FTIM2_NOR_TCH(0x4) | \ |
| 276 | FTIM2_NOR_TWPH(0x0E) | \ |
| 277 | FTIM2_NOR_TWP(0x1c)) |
| 278 | #define CONFIG_SYS_NOR_FTIM3 0x0 |
| 279 | |
| 280 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 281 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 282 | |
| 283 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 284 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 285 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 286 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 287 | |
| 288 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 289 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ |
| 290 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
| 291 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ |
| 292 | #define QIXIS_BASE 0xffdf0000 |
| 293 | #ifdef CONFIG_PHYS_64BIT |
| 294 | #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) |
| 295 | #else |
| 296 | #define QIXIS_BASE_PHYS QIXIS_BASE |
| 297 | #endif |
| 298 | #define QIXIS_LBMAP_SWITCH 0x06 |
| 299 | #define QIXIS_LBMAP_MASK 0x0f |
| 300 | #define QIXIS_LBMAP_SHIFT 0 |
| 301 | #define QIXIS_LBMAP_DFLTBANK 0x00 |
| 302 | #define QIXIS_LBMAP_ALTBANK 0x04 |
| 303 | #define QIXIS_RST_CTL_RESET 0x31 |
| 304 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
| 305 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
| 306 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
| 307 | #define QIXIS_RST_FORCE_MEM 0x01 |
| 308 | |
| 309 | #define CONFIG_SYS_CSPR3_EXT (0xf) |
| 310 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ |
| 311 | | CSPR_PORT_SIZE_8 \ |
| 312 | | CSPR_MSEL_GPCM \ |
| 313 | | CSPR_V) |
| 314 | #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) |
| 315 | #define CONFIG_SYS_CSOR3 0x0 |
| 316 | /* QIXIS Timing parameters for IFC CS3 */ |
| 317 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
| 318 | FTIM0_GPCM_TEADC(0x0e) | \ |
| 319 | FTIM0_GPCM_TEAHC(0x0e)) |
| 320 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
| 321 | FTIM1_GPCM_TRAD(0x3f)) |
| 322 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ |
| 323 | FTIM2_GPCM_TCH(0x8) | \ |
| 324 | FTIM2_GPCM_TWP(0x1f)) |
| 325 | #define CONFIG_SYS_CS3_FTIM3 0x0 |
| 326 | |
| 327 | #define CONFIG_NAND_FSL_IFC |
| 328 | #define CONFIG_SYS_NAND_BASE 0xff800000 |
| 329 | #ifdef CONFIG_PHYS_64BIT |
| 330 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) |
| 331 | #else |
| 332 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 333 | #endif |
| 334 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) |
| 335 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 336 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ |
| 337 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ |
| 338 | | CSPR_V) |
| 339 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
| 340 | |
| 341 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 342 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 343 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 344 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ |
| 345 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ |
| 346 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ |
| 347 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
| 348 | |
| 349 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 350 | |
| 351 | /* ONFI NAND Flash mode0 Timing Params */ |
| 352 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
| 353 | FTIM0_NAND_TWP(0x18) | \ |
| 354 | FTIM0_NAND_TWCHT(0x07) | \ |
| 355 | FTIM0_NAND_TWH(0x0a)) |
| 356 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
| 357 | FTIM1_NAND_TWBE(0x39) | \ |
| 358 | FTIM1_NAND_TRR(0x0e) | \ |
| 359 | FTIM1_NAND_TRP(0x18)) |
| 360 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
| 361 | FTIM2_NAND_TREH(0x0a) | \ |
| 362 | FTIM2_NAND_TWHRE(0x1e)) |
| 363 | #define CONFIG_SYS_NAND_FTIM3 0x0 |
| 364 | |
| 365 | #define CONFIG_SYS_NAND_DDR_LAW 11 |
| 366 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 367 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 368 | |
| 369 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 370 | |
| 371 | #if defined(CONFIG_NAND) |
| 372 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 373 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 374 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| 375 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| 376 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 377 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 378 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 379 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 380 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 381 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR |
| 382 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
| 383 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 384 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 385 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 386 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 387 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 388 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT |
| 389 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR |
| 390 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
| 391 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR |
| 392 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 393 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 394 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 395 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 396 | #else |
| 397 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 398 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
| 399 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 400 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 401 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 402 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 403 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 404 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 405 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT |
| 406 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR |
| 407 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
| 408 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 409 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 410 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 411 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 412 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 413 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 414 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR |
| 415 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK |
| 416 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR |
| 417 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 418 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 419 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 420 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 421 | #endif |
| 422 | |
| 423 | #ifdef CONFIG_SPL_BUILD |
| 424 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| 425 | #else |
| 426 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 427 | #endif |
| 428 | |
| 429 | #if defined(CONFIG_RAMBOOT_PBL) |
| 430 | #define CONFIG_SYS_RAMBOOT |
| 431 | #endif |
| 432 | |
| 433 | #define CONFIG_BOARD_EARLY_INIT_R |
| 434 | #define CONFIG_MISC_INIT_R |
| 435 | |
| 436 | #define CONFIG_HWCONFIG |
| 437 | |
| 438 | /* define to use L1 as initial stack */ |
| 439 | #define CONFIG_L1_INIT_RAM |
| 440 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 441 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ |
| 442 | #ifdef CONFIG_PHYS_64BIT |
| 443 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
York Sun | ee7b483 | 2015-08-17 13:31:51 -0700 | [diff] [blame] | 444 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 445 | /* The assembler doesn't like typecast */ |
| 446 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
| 447 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ |
| 448 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
| 449 | #else |
York Sun | ee7b483 | 2015-08-17 13:31:51 -0700 | [diff] [blame] | 450 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 451 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 |
| 452 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS |
| 453 | #endif |
| 454 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
| 455 | |
| 456 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 457 | GENERATED_GBL_DATA_SIZE) |
| 458 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 459 | |
| 460 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 461 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
| 462 | |
| 463 | /* Serial Port */ |
| 464 | #define CONFIG_CONS_INDEX 1 |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 465 | #define CONFIG_SYS_NS16550_SERIAL |
| 466 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 467 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
| 468 | |
| 469 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 470 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 471 | |
| 472 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) |
| 473 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) |
| 474 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) |
| 475 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 476 | |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 477 | /* Video */ |
York Sun | 7d29dd6 | 2016-11-18 13:01:34 -0800 | [diff] [blame] | 478 | #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 479 | #define CONFIG_FSL_DIU_FB |
| 480 | #ifdef CONFIG_FSL_DIU_FB |
| 481 | #define CONFIG_FSL_DIU_CH7301 |
| 482 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 483 | #define CONFIG_VIDEO_LOGO |
| 484 | #define CONFIG_VIDEO_BMP_LOGO |
| 485 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
| 486 | /* |
| 487 | * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so |
| 488 | * disable empty flash sector detection, which is I/O-intensive. |
| 489 | */ |
| 490 | #undef CONFIG_SYS_FLASH_EMPTY_INFO |
| 491 | #endif |
| 492 | #endif |
| 493 | |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 494 | /* I2C */ |
| 495 | #define CONFIG_SYS_I2C |
| 496 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ |
| 497 | #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ |
| 498 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 499 | #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ |
| 500 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 501 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
| 502 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
| 503 | |
| 504 | #define I2C_MUX_PCA_ADDR 0x77 |
| 505 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ |
Shengzhou Liu | f847bcc | 2014-11-24 17:18:28 +0800 | [diff] [blame] | 506 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ |
| 507 | #define I2C_RETIMER_ADDR 0x18 |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 508 | |
| 509 | /* I2C bus multiplexer */ |
| 510 | #define I2C_MUX_CH_DEFAULT 0x8 |
| 511 | #define I2C_MUX_CH_DIU 0xC |
Shengzhou Liu | f847bcc | 2014-11-24 17:18:28 +0800 | [diff] [blame] | 512 | #define I2C_MUX_CH5 0xD |
| 513 | #define I2C_MUX_CH7 0xF |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 514 | |
| 515 | /* LDI/DVI Encoder for display */ |
| 516 | #define CONFIG_SYS_I2C_LDI_ADDR 0x38 |
| 517 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 |
| 518 | |
| 519 | /* |
| 520 | * RTC configuration |
| 521 | */ |
| 522 | #define RTC |
| 523 | #define CONFIG_RTC_DS3231 1 |
| 524 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 525 | |
| 526 | /* |
| 527 | * eSPI - Enhanced SPI |
| 528 | */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 529 | #ifndef CONFIG_SPL_BUILD |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 530 | #endif |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 531 | #define CONFIG_SPI_FLASH_BAR |
| 532 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 533 | #define CONFIG_SF_DEFAULT_MODE 0 |
| 534 | |
| 535 | /* |
| 536 | * General PCIe |
| 537 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 538 | */ |
Robert P. J. Day | a809981 | 2016-05-03 19:52:49 -0400 | [diff] [blame] | 539 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 540 | #define CONFIG_PCIE2 /* PCIE controller 2 */ |
| 541 | #define CONFIG_PCIE3 /* PCIE controller 3 */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 542 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| 543 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| 544 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 545 | |
| 546 | #ifdef CONFIG_PCI |
| 547 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
| 548 | #ifdef CONFIG_PCIE1 |
| 549 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 550 | #ifdef CONFIG_PHYS_64BIT |
| 551 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 552 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 553 | #else |
| 554 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
| 555 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 |
| 556 | #endif |
| 557 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
| 558 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
| 559 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 560 | #ifdef CONFIG_PHYS_64BIT |
| 561 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
| 562 | #else |
| 563 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 |
| 564 | #endif |
| 565 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 566 | #endif |
| 567 | |
| 568 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ |
| 569 | #ifdef CONFIG_PCIE2 |
| 570 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 |
| 571 | #ifdef CONFIG_PHYS_64BIT |
| 572 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
| 573 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull |
| 574 | #else |
| 575 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 |
| 576 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 |
| 577 | #endif |
| 578 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
| 579 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
| 580 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 581 | #ifdef CONFIG_PHYS_64BIT |
| 582 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
| 583 | #else |
| 584 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 |
| 585 | #endif |
| 586 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 587 | #endif |
| 588 | |
| 589 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
| 590 | #ifdef CONFIG_PCIE3 |
| 591 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
| 592 | #ifdef CONFIG_PHYS_64BIT |
| 593 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| 594 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull |
| 595 | #else |
| 596 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 |
| 597 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 |
| 598 | #endif |
| 599 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ |
| 600 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
| 601 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 602 | #ifdef CONFIG_PHYS_64BIT |
| 603 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
| 604 | #else |
| 605 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 |
| 606 | #endif |
| 607 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 608 | #endif |
| 609 | |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 610 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 611 | #endif /* CONFIG_PCI */ |
| 612 | |
| 613 | /* |
| 614 | *SATA |
| 615 | */ |
| 616 | #define CONFIG_FSL_SATA_V2 |
| 617 | #ifdef CONFIG_FSL_SATA_V2 |
| 618 | #define CONFIG_LIBATA |
| 619 | #define CONFIG_FSL_SATA |
| 620 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
| 621 | #define CONFIG_SATA1 |
| 622 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| 623 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
| 624 | #define CONFIG_LBA48 |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 625 | #endif |
| 626 | |
| 627 | /* |
| 628 | * USB |
| 629 | */ |
| 630 | #define CONFIG_HAS_FSL_DR_USB |
| 631 | |
| 632 | #ifdef CONFIG_HAS_FSL_DR_USB |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 633 | #define CONFIG_USB_EHCI_FSL |
| 634 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 635 | #endif |
| 636 | |
| 637 | /* |
| 638 | * SDHC |
| 639 | */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 640 | #ifdef CONFIG_MMC |
| 641 | #define CONFIG_FSL_ESDHC |
| 642 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 643 | #endif |
| 644 | |
| 645 | /* Qman/Bman */ |
| 646 | #ifndef CONFIG_NOBQFMAN |
| 647 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
Jeffrey Ladouceur | f9c3974 | 2014-12-03 18:08:43 -0500 | [diff] [blame] | 648 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 649 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
| 650 | #ifdef CONFIG_PHYS_64BIT |
| 651 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
| 652 | #else |
| 653 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE |
| 654 | #endif |
| 655 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
Jeffrey Ladouceur | ff2c646 | 2014-12-08 14:54:01 -0500 | [diff] [blame] | 656 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 657 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 |
| 658 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE |
| 659 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) |
| 660 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ |
| 661 | CONFIG_SYS_BMAN_CENA_SIZE) |
| 662 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) |
| 663 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 |
Jeffrey Ladouceur | f9c3974 | 2014-12-03 18:08:43 -0500 | [diff] [blame] | 664 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 665 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
| 666 | #ifdef CONFIG_PHYS_64BIT |
| 667 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
| 668 | #else |
| 669 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE |
| 670 | #endif |
| 671 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
Jeffrey Ladouceur | ff2c646 | 2014-12-08 14:54:01 -0500 | [diff] [blame] | 672 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 673 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 |
| 674 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE |
| 675 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) |
| 676 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ |
| 677 | CONFIG_SYS_QMAN_CENA_SIZE) |
| 678 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) |
| 679 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 680 | |
| 681 | #define CONFIG_SYS_DPAA_FMAN |
| 682 | |
| 683 | #define CONFIG_QE |
| 684 | #define CONFIG_U_QE |
| 685 | /* Default address of microcode for the Linux FMan driver */ |
| 686 | #if defined(CONFIG_SPIFLASH) |
| 687 | /* |
| 688 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after |
| 689 | * env, so we got 0x110000. |
| 690 | */ |
| 691 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH |
| 692 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
| 693 | #define CONFIG_SYS_QE_FW_ADDR 0x130000 |
| 694 | #elif defined(CONFIG_SDCARD) |
| 695 | /* |
| 696 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is |
| 697 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
| 698 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). |
| 699 | */ |
| 700 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
| 701 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
| 702 | #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) |
| 703 | #elif defined(CONFIG_NAND) |
| 704 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
| 705 | #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 706 | #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 707 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
| 708 | /* |
| 709 | * Slave has no ucode locally, it can fetch this from remote. When implementing |
| 710 | * in two corenet boards, slave's ucode could be stored in master's memory |
| 711 | * space, the address can be mapped from slave TLB->slave LAW-> |
| 712 | * slave SRIO or PCIE outbound window->master inbound window-> |
| 713 | * master LAW->the ucode address in master's memory space. |
| 714 | */ |
| 715 | #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE |
| 716 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
| 717 | #else |
| 718 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
| 719 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
| 720 | #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 |
| 721 | #endif |
| 722 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 723 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
| 724 | #endif /* CONFIG_NOBQFMAN */ |
| 725 | |
| 726 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 727 | #define CONFIG_FMAN_ENET |
| 728 | #define CONFIG_PHYLIB_10G |
| 729 | #define CONFIG_PHY_VITESSE |
| 730 | #define CONFIG_PHY_REALTEK |
| 731 | #define CONFIG_PHY_TERANETICS |
| 732 | #define RGMII_PHY1_ADDR 0x1 |
| 733 | #define RGMII_PHY2_ADDR 0x2 |
| 734 | #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 |
| 735 | #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 |
| 736 | #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 |
| 737 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C |
| 738 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1D |
| 739 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E |
| 740 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F |
| 741 | #endif |
| 742 | |
| 743 | #ifdef CONFIG_FMAN_ENET |
| 744 | #define CONFIG_MII /* MII PHY management */ |
| 745 | #define CONFIG_ETHPRIME "FM1@DTSEC4" |
| 746 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
| 747 | #endif |
| 748 | |
| 749 | /* |
| 750 | * Dynamic MTD Partition support with mtdparts |
| 751 | */ |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 752 | #ifdef CONFIG_MTD_NOR_FLASH |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 753 | #define CONFIG_MTD_DEVICE |
| 754 | #define CONFIG_MTD_PARTITIONS |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 755 | #define CONFIG_FLASH_CFI_MTD |
| 756 | #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ |
| 757 | "spi0=spife110000.0" |
| 758 | #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ |
| 759 | "128k(dtb),96m(fs),-(user);"\ |
| 760 | "fff800000.flash:2m(uboot),9m(kernel),"\ |
| 761 | "128k(dtb),96m(fs),-(user);spife110000.0:" \ |
| 762 | "2m(uboot),9m(kernel),128k(dtb),-(user)" |
| 763 | #endif |
| 764 | |
| 765 | /* |
| 766 | * Environment |
| 767 | */ |
| 768 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
| 769 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
| 770 | |
| 771 | /* |
| 772 | * Command line configuration. |
| 773 | */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 774 | #define CONFIG_CMD_REGINFO |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 775 | |
| 776 | #ifdef CONFIG_PCI |
| 777 | #define CONFIG_CMD_PCI |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 778 | #endif |
| 779 | |
| 780 | /* |
| 781 | * Miscellaneous configurable options |
| 782 | */ |
| 783 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 784 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 785 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| 786 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 787 | #ifdef CONFIG_CMD_KGDB |
| 788 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 789 | #else |
| 790 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 791 | #endif |
| 792 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 793 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 794 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 795 | |
| 796 | /* |
| 797 | * For booting Linux, the board info and command line data |
| 798 | * have to be in the first 64 MB of memory, since this is |
| 799 | * the maximum mapped by the Linux kernel during initialization. |
| 800 | */ |
| 801 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ |
| 802 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 803 | |
| 804 | #ifdef CONFIG_CMD_KGDB |
| 805 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 806 | #endif |
| 807 | |
| 808 | /* |
| 809 | * Environment Configuration |
| 810 | */ |
| 811 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| 812 | #define CONFIG_BOOTFILE "uImage" |
| 813 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ |
| 814 | #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 815 | #define __USB_PHY_TYPE utmi |
| 816 | |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 817 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 818 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ |
| 819 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ |
| 820 | "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ |
| 821 | "ramdiskfile=t1024qds/ramdisk.uboot\0" \ |
| 822 | "fdtfile=t1024qds/t1024qds.dtb\0" \ |
| 823 | "netdev=eth0\0" \ |
| 824 | "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ |
| 825 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 826 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ |
| 827 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
| 828 | "protect off $ubootaddr +$filesize && " \ |
| 829 | "erase $ubootaddr +$filesize && " \ |
| 830 | "cp.b $loadaddr $ubootaddr $filesize && " \ |
| 831 | "protect on $ubootaddr +$filesize && " \ |
| 832 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ |
| 833 | "consoledev=ttyS0\0" \ |
| 834 | "ramdiskaddr=2000000\0" \ |
| 835 | "fdtaddr=d00000\0" \ |
| 836 | "bdev=sda3\0" |
| 837 | |
| 838 | #define CONFIG_LINUX \ |
| 839 | "setenv bootargs root=/dev/ram rw " \ |
| 840 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 841 | "setenv ramdiskaddr 0x02000000;" \ |
| 842 | "setenv fdtaddr 0x00c00000;" \ |
| 843 | "setenv loadaddr 0x1000000;" \ |
| 844 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 845 | |
| 846 | #define CONFIG_NFSBOOTCOMMAND \ |
| 847 | "setenv bootargs root=/dev/nfs rw " \ |
| 848 | "nfsroot=$serverip:$rootpath " \ |
| 849 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 850 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 851 | "tftp $loadaddr $bootfile;" \ |
| 852 | "tftp $fdtaddr $fdtfile;" \ |
| 853 | "bootm $loadaddr - $fdtaddr" |
| 854 | |
| 855 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX |
| 856 | |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 857 | #include <asm/fsl_secure_boot.h> |
Aneesh Bansal | 962021a | 2016-01-22 16:37:22 +0530 | [diff] [blame] | 858 | |
Shengzhou Liu | 9eca55f | 2014-11-24 17:11:55 +0800 | [diff] [blame] | 859 | #endif /* __T1024QDS_H */ |