Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 1 | /* |
Albert ARIBAUD | 340983d | 2011-04-22 19:41:02 +0200 | [diff] [blame] | 2 | * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 3 | * |
Albert ARIBAUD | 340983d | 2011-04-22 19:41:02 +0200 | [diff] [blame] | 4 | * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net> |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 22 | * MA 02110-1301 USA |
| 23 | */ |
| 24 | |
| 25 | #include <common.h> |
| 26 | #include <asm/io.h> |
| 27 | |
| 28 | #if defined(CONFIG_ORION5X) |
| 29 | #include <asm/arch/orion5x.h> |
| 30 | #elif defined(CONFIG_KIRKWOOD) |
| 31 | #include <asm/arch/kirkwood.h> |
| 32 | #endif |
| 33 | |
| 34 | /* SATA port registers */ |
| 35 | struct mvsata_port_registers { |
| 36 | u32 reserved1[192]; |
| 37 | /* offset 0x300 : ATA Interface registers */ |
| 38 | u32 sstatus; |
| 39 | u32 serror; |
| 40 | u32 scontrol; |
| 41 | u32 ltmode; |
| 42 | u32 phymode3; |
| 43 | u32 phymode4; |
| 44 | u32 reserved2[5]; |
| 45 | u32 phymode1; |
| 46 | u32 phymode2; |
| 47 | u32 bist_cr; |
| 48 | u32 bist_dw1; |
| 49 | u32 bist_dw2; |
| 50 | u32 serrorintrmask; |
| 51 | }; |
| 52 | |
| 53 | /* |
| 54 | * Sanity checks: |
| 55 | * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR. |
| 56 | * - for ide_preinit to make sense, we need at least one of |
| 57 | * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE0_OFFSET; |
| 58 | * - for inde_preinit to be called, we need CONFIG_IDE_PREINIT. |
| 59 | * Fail with an explanation message if these conditions are not met. |
| 60 | * This is particularly important for CONFIG_IDE_PREINIT, because |
| 61 | * its lack would not cause a build error. |
| 62 | */ |
| 63 | |
| 64 | #if !defined(CONFIG_SYS_ATA_BASE_ADDR) |
| 65 | #error CONFIG_SYS_ATA_BASE_ADDR must be defined |
| 66 | #elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \ |
| 67 | && !defined(CONFIG_SYS_ATA_IDE1_OFFSET) |
| 68 | #error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \ |
| 69 | must be defined |
| 70 | #elif !defined(CONFIG_IDE_PREINIT) |
| 71 | #error CONFIG_IDE_PREINIT must be defined |
| 72 | #endif |
| 73 | |
| 74 | /* |
| 75 | * Masks and values for SControl DETection and Interface Power Management, |
| 76 | * and for SStatus DETection. |
| 77 | */ |
| 78 | |
| 79 | #define MVSATA_SCONTROL_DET_MASK 0x0000000F |
| 80 | #define MVSATA_SCONTROL_DET_NONE 0x00000000 |
| 81 | #define MVSATA_SCONTROL_DET_INIT 0x00000001 |
| 82 | #define MVSATA_SCONTROL_IPM_MASK 0x00000F00 |
| 83 | #define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED 0x00000300 |
| 84 | #define MVSATA_SCONTROL_MASK \ |
| 85 | (MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK) |
| 86 | #define MVSATA_PORT_INIT \ |
| 87 | (MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED) |
| 88 | #define MVSATA_PORT_USE \ |
| 89 | (MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED) |
| 90 | #define MVSATA_SSTATUS_DET_MASK 0x0000000F |
| 91 | #define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003 |
| 92 | |
| 93 | /* |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 94 | * Status codes to return to client callers. Currently, callers ignore |
| 95 | * exact value and only care for zero or nonzero, so no need to make this |
| 96 | * public, it is only #define'd for clarity. |
| 97 | * If/when standard negative codes are implemented in U-boot, then these |
| 98 | * #defines should be moved to, or replaced by ones from, the common list |
| 99 | * of status codes. |
| 100 | */ |
| 101 | |
| 102 | #define MVSATA_STATUS_OK 0 |
| 103 | #define MVSATA_STATUS_TIMEOUT -1 |
| 104 | |
| 105 | /* |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 106 | * Initialize one MVSATAHC port: set SControl's IPM to "always active" |
| 107 | * and DET to "reset", then wait for SStatus's DET to become "device and |
| 108 | * comm ok" (or time out after 50 us if no device), then set SControl's |
| 109 | * DET back to "no action". |
| 110 | */ |
| 111 | |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 112 | static int mvsata_ide_initialize_port(struct mvsata_port_registers *port) |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 113 | { |
| 114 | u32 control; |
| 115 | u32 status; |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 116 | u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */ |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 117 | |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 118 | /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */ |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 119 | control = readl(&port->scontrol); |
| 120 | control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT; |
| 121 | writel(control, &port->scontrol); |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 122 | /* Toggle control DET back to 0 (normal operation) */ |
| 123 | control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; |
| 124 | writel(control, &port->scontrol); |
| 125 | /* wait for status DET to become 3 (device and communication OK) */ |
| 126 | while (--timeleft) { |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 127 | status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK; |
| 128 | if (status == MVSATA_SSTATUS_DET_DEVCOMM) |
| 129 | break; |
| 130 | udelay(1); |
| 131 | } |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 132 | /* return success or time-out error depending on time left */ |
| 133 | if (!timeleft) |
| 134 | return MVSATA_STATUS_TIMEOUT; |
| 135 | return MVSATA_STATUS_OK; |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | /* |
| 139 | * ide_preinit() will be called by ide_init in cmd_ide.c and will |
| 140 | * reset the MVSTATHC ports needed by the board. |
| 141 | */ |
| 142 | |
| 143 | int ide_preinit(void) |
| 144 | { |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 145 | int status; |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 146 | /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ |
| 147 | #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 148 | status = mvsata_ide_initialize_port( |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 149 | (struct mvsata_port_registers *) |
| 150 | (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET)); |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 151 | if (status) |
| 152 | return status; |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 153 | #endif |
| 154 | /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */ |
| 155 | #if defined(CONFIG_SYS_ATA_IDE1_OFFSET) |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 156 | status = mvsata_ide_initialize_port( |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 157 | (struct mvsata_port_registers *) |
| 158 | (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET)); |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 159 | if (status) |
| 160 | return status; |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 161 | #endif |
Albert Aribaud | a1bd9c5 | 2010-09-16 20:30:30 +0530 | [diff] [blame] | 162 | /* return success if all ports initializations succeeded */ |
| 163 | return MVSATA_STATUS_OK; |
Albert Aribaud | 89a1ef0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 164 | } |