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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Valentin Longchampc98bf292013-10-18 11:47:24 +02002/*
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
Valentin Longchampc98bf292013-10-18 11:47:24 +02005 */
6
7#include <common.h>
Simon Glass274e0b02020-05-10 11:39:56 -06008#include <net.h>
Valentin Longchampc98bf292013-10-18 11:47:24 +02009#include <netdev.h>
10#include <fm_eth.h>
11#include <fsl_mdio.h>
12#include <phy.h>
13
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090014int board_eth_init(struct bd_info *bis)
Valentin Longchampc98bf292013-10-18 11:47:24 +020015{
16 int ret = 0;
17#ifdef CONFIG_FMAN_ENET
18 struct fsl_pq_mdio_info dtsec_mdio_info;
19
20 printf("Initializing Fman\n");
21
22 dtsec_mdio_info.regs =
23 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
24 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
25
26 /* Register the real 1G MDIO bus */
27 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
28
29 /* DTESC1/2 don't have a PHY, they are temporarily disabled
30 * so that u-boot doesn't try to unsuccessfuly enable them */
31 fm_disable_port(FM1_DTSEC1);
32 fm_disable_port(FM1_DTSEC2);
33
34 /*
35 * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf
36 * This is the debug interface, the only one used in u-boot
37 */
38 fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
39 fm_info_set_mdio(FM1_DTSEC5,
40 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
41
42 ret = cpu_eth_init(bis);
43
44 /* reenable DTSEC1/2 for later (kernel) */
45 fm_enable_port(FM1_DTSEC1);
46 fm_enable_port(FM1_DTSEC2);
47#endif
48
49 return ret;
50}
51
52#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL)
53
54#define mv88E1118_PAGE_REG 22
55
56int board_phy_config(struct phy_device *phydev)
57{
58 if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) {
59 /* driver config is good */
60 if (phydev->drv->config)
61 phydev->drv->config(phydev);
62
63 /* but we still need to fix the LEDs */
64 phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003);
65 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840);
66 phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000);
67 }
68
69 return 0;
70}
71#endif