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Wolfgang Denkb38e0df2007-03-06 18:08:43 +01001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkb38e0df2007-03-06 18:08:43 +01006 */
7
8#include <common.h>
9
10/*
11 * CPU test
12 * Load/store string instructions: lswi, stswi, lswx, stswx
13 *
14 * Several consecutive bytes from a source memory buffer are loaded
15 * left to right into GPRs. After that, the bytes are stored
16 * from the GPRs into a target memory buffer. The contents
17 * of the source and target buffers are then compared.
18 */
19
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010020#include <post.h>
21#include "cpu_asm.h"
22
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020023#if CONFIG_POST & CONFIG_SYS_POST_CPU
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010024
25extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2);
26extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3,
27 ulong op4);
28
29#include <bedbug/regs.h>
30int cpu_post_test_string (void)
31{
32 int ret = 0;
33 unsigned int i;
Stefan Roese37628252008-08-06 14:05:38 +020034 int flag = disable_interrupts();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010035
36 if (ret == 0)
37 {
38 char src [31], dst [31];
39
40 ulong code[] =
41 {
42 ASM_LSWI(5, 3, 31),
43 ASM_STSWI(5, 4, 31),
44 ASM_BLR,
45 };
46
47 for (i = 0; i < sizeof(src); i ++)
48 {
49 src[i] = (char) i;
50 dst[i] = 0;
51 }
52
53 cpu_post_exec_02(code, (ulong)src, (ulong)dst);
54
55 ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1;
56 }
57
58 if (ret == 0)
59 {
60 char src [95], dst [95];
61
62 ulong code[] =
63 {
64 ASM_LSWX(8, 3, 5),
65 ASM_STSWX(8, 4, 5),
66 ASM_BLR,
67 };
68
69 for (i = 0; i < sizeof(src); i ++)
70 {
71 src[i] = (char) i;
72 dst[i] = 0;
73 }
74
75 cpu_post_exec_04(code, (ulong)src, (ulong)dst, 0, sizeof(src));
76
77 ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1;
78 }
79
80 if (ret != 0)
81 {
82 post_log ("Error at string test !\n");
83 }
84
Stefan Roese37628252008-08-06 14:05:38 +020085 if (flag)
86 enable_interrupts();
87
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010088 return ret;
89}
90
91#endif