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FUKAUMI Naoki4913ee92024-07-17 13:47:24 +09001/* SPDX-License-Identifier: GPL-2.0+ */
Joseph Chen72cd8792021-06-02 15:58:25 +08002/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __CONFIG_RK3568_COMMON_H
7#define __CONFIG_RK3568_COMMON_H
8
Jonas Karlmanbe56bb52023-02-22 22:44:41 +00009#define CFG_CPUID_OFFSET 0xa
10
Joseph Chen72cd8792021-06-02 15:58:25 +080011#include "rockchip-common.h"
12
FUKAUMI Naoki4913ee92024-07-17 13:47:24 +090013#define CFG_IRAM_BASE 0xfdcc0000
Joseph Chen72cd8792021-06-02 15:58:25 +080014
Tom Rinibb4dd962022-11-16 13:10:37 -050015#define CFG_SYS_SDRAM_BASE 0
Joseph Chen72cd8792021-06-02 15:58:25 +080016#define SDRAM_MAX_SIZE 0xf0000000
17
Joseph Chen72cd8792021-06-02 15:58:25 +080018#define ENV_MEM_LAYOUT_SETTINGS \
19 "scriptaddr=0x00c00000\0" \
Jonas Karlmanf4d27e92023-04-17 19:07:17 +000020 "script_offset_f=0xffe000\0" \
21 "script_size_f=0x2000\0" \
Joseph Chen72cd8792021-06-02 15:58:25 +080022 "pxefile_addr_r=0x00e00000\0" \
Hugh Cole-Bakerdc368eb2023-12-26 16:43:30 +000023 "kernel_addr_r=0x02000000\0" \
24 "kernel_comp_addr_r=0x0a000000\0" \
25 "fdt_addr_r=0x12000000\0" \
26 "fdtoverlay_addr_r=0x12100000\0" \
27 "ramdisk_addr_r=0x12180000\0" \
28 "kernel_comp_size=0x8000000\0"
Joseph Chen72cd8792021-06-02 15:58:25 +080029
Tom Rinic9edebe2022-12-04 10:03:50 -050030#define CFG_EXTRA_ENV_SETTINGS \
FUKAUMI Naoki4913ee92024-07-17 13:47:24 +090031 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
32 "partitions=" PARTS_DEFAULT \
33 ENV_MEM_LAYOUT_SETTINGS \
34 ROCKCHIP_DEVICE_SETTINGS \
Simon Glassf27e9d52023-04-24 13:49:51 +120035 "boot_targets=" BOOT_TARGETS "\0"
Joseph Chen72cd8792021-06-02 15:58:25 +080036
FUKAUMI Naoki4913ee92024-07-17 13:47:24 +090037#endif /* __CONFIG_RK3568_COMMON_H */